Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description

[Alistair Francis <alistair23@gmail.com>]

On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Add a subsection to machine.c to migrate debug CSR state.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - new patch: add debug state description
>
>  target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 5178b3fec9..4921dad09d 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
>          VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
>          VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
>          VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
> +static bool debug_needed(void *opaque)
> +{
> +    RISCVCPU *cpu = opaque;
> +    CPURISCVState *env = &cpu->env;
> +
> +    return riscv_feature(env, RISCV_FEATURE_DEBUG);

This fails to build:

../target/riscv/machine.c: In function ‘debug_needed’:
../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’
undeclared (first use in this function); did you mean
‘RISCV_FEATURE_EPMP’?
 228 |     return riscv_feature(env, RISCV_FEATURE_DEBUG);
     |                               ^~~~~~~~~~~~~~~~~~~
     |                               RISCV_FEATURE_EPMP
../target/riscv/machine.c:228:31: note: each undeclared identifier is
reported only once for each function it appears in
../target/riscv/machine.c:229:1: warning: control reaches end of
non-void function [-Wreturn-type]
 229 | }
     | ^

Alistair

> +}
>
> +static const VMStateDescription vmstate_debug_type2 = {
> +    .name = "cpu/debug/type2",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINTTL(mcontrol, type2_trigger_t),
> +        VMSTATE_UINTTL(maddress, type2_trigger_t),
> +        VMSTATE_END_OF_LIST()
> +   }
> +};
> +
> +static const VMStateDescription vmstate_debug = {
> +    .name = "cpu/debug",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = debug_needed,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
> +        VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
> +                             0, vmstate_debug_type2, type2_trigger_t),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> @@ -292,6 +323,7 @@ const VMStateDescription vmstate_riscv_cpu = {
>          &vmstate_pointermasking,
>          &vmstate_rv128,
>          &vmstate_kvmtimer,
> +        &vmstate_debug,
>          NULL
>      }
>  };
> --
> 2.25.1
>
>