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Wed, 20 Apr 2022 00:31:20 -0700 (PDT) MIME-Version: 1.0 References: <20220315065529.62198-1-bmeng.cn@gmail.com> <20220315065529.62198-3-bmeng.cn@gmail.com> In-Reply-To: <20220315065529.62198-3-bmeng.cn@gmail.com> From: Alistair Francis Date: Wed, 20 Apr 2022 17:30:54 +1000 Message-ID: Subject: Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description To: Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=alistair23@gmail.com; helo=mail-io1-xd2d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Alistair Francis , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Mar 15, 2022 at 5:17 PM Bin Meng wrote: > > From: Bin Meng > > Add a subsection to machine.c to migrate debug CSR state. > > Signed-off-by: Bin Meng > Reviewed-by: Alistair Francis > --- > > (no changes since v2) > > Changes in v2: > - new patch: add debug state description > > target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 5178b3fec9..4921dad09d 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer =3D= { > VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), > VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), > VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static bool debug_needed(void *opaque) > +{ > + RISCVCPU *cpu =3D opaque; > + CPURISCVState *env =3D &cpu->env; > + > + return riscv_feature(env, RISCV_FEATURE_DEBUG); This fails to build: ../target/riscv/machine.c: In function =E2=80=98debug_needed=E2=80=99: ../target/riscv/machine.c:228:31: error: =E2=80=98RISCV_FEATURE_DEBUG=E2=80= =99 undeclared (first use in this function); did you mean =E2=80=98RISCV_FEATURE_EPMP=E2=80=99? 228 | return riscv_feature(env, RISCV_FEATURE_DEBUG); | ^~~~~~~~~~~~~~~~~~~ | RISCV_FEATURE_EPMP ../target/riscv/machine.c:228:31: note: each undeclared identifier is reported only once for each function it appears in ../target/riscv/machine.c:229:1: warning: control reaches end of non-void function [-Wreturn-type] 229 | } | ^ Alistair > +} > > +static const VMStateDescription vmstate_debug_type2 =3D { > + .name =3D "cpu/debug/type2", > + .version_id =3D 1, > + .minimum_version_id =3D 1, > + .fields =3D (VMStateField[]) { > + VMSTATE_UINTTL(mcontrol, type2_trigger_t), > + VMSTATE_UINTTL(maddress, type2_trigger_t), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static const VMStateDescription vmstate_debug =3D { > + .name =3D "cpu/debug", > + .version_id =3D 1, > + .minimum_version_id =3D 1, > + .needed =3D debug_needed, > + .fields =3D (VMStateField[]) { > + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), > + VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM= , > + 0, vmstate_debug_type2, type2_trigger_t), > VMSTATE_END_OF_LIST() > } > }; > @@ -292,6 +323,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { > &vmstate_pointermasking, > &vmstate_rv128, > &vmstate_kvmtimer, > + &vmstate_debug, > NULL > } > }; > -- > 2.25.1 > >