* [PATCH v4 1/3] hw/misc: Implement STM32L4x5 SYSCFG
2024-01-09 19:41 [PATCH v4 0/3] Add device STM32L4x5 SYSCFG Inès Varhol
@ 2024-01-09 19:41 ` Inès Varhol
2024-01-09 19:41 ` [PATCH v4 2/3] hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC Inès Varhol
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Inès Varhol @ 2024-01-09 19:41 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Alistair Francis, Samuel Tardieu, Peter Maydell,
qemu-arm, Paolo Bonzini, Arnaud Minier,
Philippe Mathieu-Daudé, Inès Varhol, Laurent Vivier,
Alistair Francis
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
docs/system/arm/b-l475e-iot01a.rst | 2 +-
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/stm32l4x5_syscfg.c | 266 +++++++++++++++++++++++++++++
hw/misc/trace-events | 6 +
include/hw/misc/stm32l4x5_syscfg.h | 54 ++++++
6 files changed, 331 insertions(+), 1 deletion(-)
create mode 100644 hw/misc/stm32l4x5_syscfg.c
create mode 100644 include/hw/misc/stm32l4x5_syscfg.h
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
index 72f256ace7..1a021b306a 100644
--- a/docs/system/arm/b-l475e-iot01a.rst
+++ b/docs/system/arm/b-l475e-iot01a.rst
@@ -16,6 +16,7 @@ Currently B-L475E-IOT01A machine's only supports the following devices:
- Cortex-M4F based STM32L4x5 SoC
- STM32L4x5 EXTI (Extended interrupts and events controller)
+- STM32L4x5 SYSCFG (System configuration controller)
Missing devices
"""""""""""""""
@@ -24,7 +25,6 @@ The B-L475E-IOT01A does *not* support the following devices:
- Reset and clock control (RCC)
- Serial ports (UART)
-- System configuration controller (SYSCFG)
- General-purpose I/Os (GPIO)
- Analog to Digital Converter (ADC)
- SPI controller
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 3efe3dc2cc..4fc6b29b43 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -90,6 +90,9 @@ config STM32F4XX_EXTI
config STM32L4X5_EXTI
bool
+config STM32L4X5_SYSCFG
+ bool
+
config MIPS_ITU
bool
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 16db6e228d..2ca2ce4b62 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -111,6 +111,7 @@ system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
system_ss.add(when: 'CONFIG_STM32L4X5_EXTI', if_true: files('stm32l4x5_exti.c'))
+system_ss.add(when: 'CONFIG_STM32L4X5_SYSCFG', if_true: files('stm32l4x5_syscfg.c'))
system_ss.add(when: 'CONFIG_MPS2_FPGAIO', if_true: files('mps2-fpgaio.c'))
system_ss.add(when: 'CONFIG_MPS2_SCC', if_true: files('mps2-scc.c'))
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
new file mode 100644
index 0000000000..fd68cb800b
--- /dev/null
+++ b/hw/misc/stm32l4x5_syscfg.c
@@ -0,0 +1,266 @@
+/*
+ * STM32L4x5 SYSCFG (System Configuration Controller)
+ *
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * This work is based on the stm32f4xx_syscfg by Alistair Francis.
+ * Original code is licensed under the MIT License:
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ */
+
+/*
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "hw/misc/stm32l4x5_syscfg.h"
+
+#define SYSCFG_MEMRMP 0x00
+#define SYSCFG_CFGR1 0x04
+#define SYSCFG_EXTICR1 0x08
+#define SYSCFG_EXTICR2 0x0C
+#define SYSCFG_EXTICR3 0x10
+#define SYSCFG_EXTICR4 0x14
+#define SYSCFG_SCSR 0x18
+#define SYSCFG_CFGR2 0x1C
+#define SYSCFG_SWPR 0x20
+#define SYSCFG_SKR 0x24
+#define SYSCFG_SWPR2 0x28
+
+/* 00000000_00000000_00000001_00000111 */
+#define ACTIVABLE_BITS_MEMRP 0x00000107
+
+/* 11111100_11111111_00000001_00000000 */
+#define ACTIVABLE_BITS_CFGR1 0xFCFF0100
+/* 00000000_00000000_00000000_00000001 */
+#define FIREWALL_DISABLE_CFGR1 0x00000001
+
+/* 00000000_00000000_11111111_11111111 */
+#define ACTIVABLE_BITS_EXTICR 0x0000FFFF
+
+/* 00000000_00000000_00000000_00000011 */
+/* #define ACTIVABLE_BITS_SCSR 0x00000003 */
+
+/* 00000000_00000000_00000000_00001111 */
+#define ECC_LOCK_CFGR2 0x0000000F
+/* 00000000_00000000_00000001_00000000 */
+#define SRAM2_PARITY_ERROR_FLAG_CFGR2 0x00000100
+
+/* 00000000_00000000_00000000_11111111 */
+#define ACTIVABLE_BITS_SKR 0x000000FF
+
+#define NUM_LINES_PER_EXTICR_REG 4
+
+static void stm32l4x5_syscfg_hold_reset(Object *obj)
+{
+ Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj);
+
+ s->memrmp = 0x00000000;
+ s->cfgr1 = 0x7C000001;
+ s->exticr[0] = 0x00000000;
+ s->exticr[1] = 0x00000000;
+ s->exticr[2] = 0x00000000;
+ s->exticr[3] = 0x00000000;
+ s->scsr = 0x00000000;
+ s->cfgr2 = 0x00000000;
+ s->swpr = 0x00000000;
+ s->skr = 0x00000000;
+ s->swpr2 = 0x00000000;
+}
+
+static void stm32l4x5_syscfg_set_irq(void *opaque, int irq, int level)
+{
+ Stm32l4x5SyscfgState *s = opaque;
+ const uint8_t gpio = irq / GPIO_NUM_PINS;
+ const int line = irq % GPIO_NUM_PINS;
+
+ const int exticr_reg = line / NUM_LINES_PER_EXTICR_REG;
+ const int startbit = (line % NUM_LINES_PER_EXTICR_REG) * 4;
+
+ g_assert(gpio < NUM_GPIOS);
+ trace_stm32l4x5_syscfg_set_irq(gpio, line, level);
+
+ if (extract32(s->exticr[exticr_reg], startbit, 4) == gpio) {
+ trace_stm32l4x5_syscfg_forward_exti(line);
+ qemu_set_irq(s->gpio_out[line], level);
+ }
+}
+
+static uint64_t stm32l4x5_syscfg_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ Stm32l4x5SyscfgState *s = opaque;
+
+ trace_stm32l4x5_syscfg_read(addr);
+
+ switch (addr) {
+ case SYSCFG_MEMRMP:
+ return s->memrmp;
+ case SYSCFG_CFGR1:
+ return s->cfgr1;
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
+ return s->exticr[(addr - SYSCFG_EXTICR1) / 4];
+ case SYSCFG_SCSR:
+ return s->scsr;
+ case SYSCFG_CFGR2:
+ return s->cfgr2;
+ case SYSCFG_SWPR:
+ return s->swpr;
+ case SYSCFG_SKR:
+ return s->skr;
+ case SYSCFG_SWPR2:
+ return s->swpr2;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+ }
+}
+static void stm32l4x5_syscfg_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned int size)
+{
+ Stm32l4x5SyscfgState *s = opaque;
+
+ trace_stm32l4x5_syscfg_write(addr, value);
+
+ switch (addr) {
+ case SYSCFG_MEMRMP:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Changing the memory mapping isn't supported\n",
+ __func__);
+ s->memrmp = value & ACTIVABLE_BITS_MEMRP;
+ return;
+ case SYSCFG_CFGR1:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Functions in CFGRx aren't supported\n",
+ __func__);
+ /* bit 0 (firewall dis.) is cleared by software, set only by reset. */
+ s->cfgr1 = (s->cfgr1 & value & FIREWALL_DISABLE_CFGR1) |
+ (value & ACTIVABLE_BITS_CFGR1);
+ return;
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
+ s->exticr[(addr - SYSCFG_EXTICR1) / 4] =
+ (value & ACTIVABLE_BITS_EXTICR);
+ return;
+ case SYSCFG_SCSR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Erasing SRAM2 isn't supported\n",
+ __func__);
+ /*
+ * only non reserved bits are :
+ * bit 0 (write-protected by a passkey), bit 1 (meant to be read)
+ * so it serves no purpose yet to add :
+ * s->scsr = value & 0x3;
+ */
+ return;
+ case SYSCFG_CFGR2:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Functions in CFGRx aren't supported\n",
+ __func__);
+ /* bit 8 (SRAM2 PEF) is cleared by software by writing a '1'.*/
+ /* bits[3:0] (ECC Lock) are set by software, cleared only by reset.*/
+ s->cfgr2 = (s->cfgr2 | (value & ECC_LOCK_CFGR2)) &
+ ~(value & SRAM2_PARITY_ERROR_FLAG_CFGR2);
+ return;
+ case SYSCFG_SWPR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Write protecting SRAM2 isn't supported\n",
+ __func__);
+ /* These bits are set by software and cleared only by reset.*/
+ s->swpr |= value;
+ return;
+ case SYSCFG_SKR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Erasing SRAM2 isn't supported\n",
+ __func__);
+ s->skr = value & ACTIVABLE_BITS_SKR;
+ return;
+ case SYSCFG_SWPR2:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Write protecting SRAM2 isn't supported\n",
+ __func__);
+ /* These bits are set by software and cleared only by reset.*/
+ s->swpr2 |= value;
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32l4x5_syscfg_ops = {
+ .read = stm32l4x5_syscfg_read,
+ .write = stm32l4x5_syscfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .impl.unaligned = false,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .valid.unaligned = false,
+};
+
+static void stm32l4x5_syscfg_init(Object *obj)
+{
+ Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj);
+
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_syscfg_ops, s,
+ TYPE_STM32L4X5_SYSCFG, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_syscfg_set_irq,
+ GPIO_NUM_PINS * NUM_GPIOS);
+ qdev_init_gpio_out(DEVICE(obj), s->gpio_out, GPIO_NUM_PINS);
+}
+
+static const VMStateDescription vmstate_stm32l4x5_syscfg = {
+ .name = TYPE_STM32L4X5_SYSCFG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(memrmp, Stm32l4x5SyscfgState),
+ VMSTATE_UINT32(cfgr1, Stm32l4x5SyscfgState),
+ VMSTATE_UINT32_ARRAY(exticr, Stm32l4x5SyscfgState,
+ SYSCFG_NUM_EXTICR),
+ VMSTATE_UINT32(scsr, Stm32l4x5SyscfgState),
+ VMSTATE_UINT32(cfgr2, Stm32l4x5SyscfgState),
+ VMSTATE_UINT32(swpr, Stm32l4x5SyscfgState),
+ VMSTATE_UINT32(skr, Stm32l4x5SyscfgState),
+ VMSTATE_UINT32(swpr2, Stm32l4x5SyscfgState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32l4x5_syscfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ dc->vmsd = &vmstate_stm32l4x5_syscfg;
+ rc->phases.hold = stm32l4x5_syscfg_hold_reset;
+}
+
+static const TypeInfo stm32l4x5_syscfg_info[] = {
+ {
+ .name = TYPE_STM32L4X5_SYSCFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Stm32l4x5SyscfgState),
+ .instance_init = stm32l4x5_syscfg_init,
+ .class_init = stm32l4x5_syscfg_class_init,
+ }
+};
+
+DEFINE_TYPES(stm32l4x5_syscfg_info)
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index fccd3204bf..5f5bc92222 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -163,6 +163,12 @@ stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+# stm32l4x5_syscfg.c
+stm32l4x5_syscfg_set_irq(int gpio, int line, int level) "irq from GPIO: %d, line: %d, level: %d"
+stm32l4x5_syscfg_forward_exti(int irq) "irq %d forwarded to EXTI"
+stm32l4x5_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
+stm32l4x5_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+
# stm32l4x5_exti.c
stm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
stm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
new file mode 100644
index 0000000000..29c3522f9d
--- /dev/null
+++ b/include/hw/misc/stm32l4x5_syscfg.h
@@ -0,0 +1,54 @@
+/*
+ * STM32L4x5 SYSCFG (System Configuration Controller)
+ *
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * This work is based on the stm32f4xx_syscfg by Alistair Francis.
+ * Original code is licensed under the MIT License:
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ */
+
+/*
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#ifndef HW_STM32L4X5_SYSCFG_H
+#define HW_STM32L4X5_SYSCFG_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
+
+#define NUM_GPIOS 8
+#define GPIO_NUM_PINS 16
+#define SYSCFG_NUM_EXTICR 4
+
+struct Stm32l4x5SyscfgState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ uint32_t memrmp;
+ uint32_t cfgr1;
+ uint32_t exticr[SYSCFG_NUM_EXTICR];
+ uint32_t scsr;
+ uint32_t cfgr2;
+ uint32_t swpr;
+ uint32_t skr;
+ uint32_t swpr2;
+
+ qemu_irq gpio_out[GPIO_NUM_PINS];
+};
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v4 2/3] hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC
2024-01-09 19:41 [PATCH v4 0/3] Add device STM32L4x5 SYSCFG Inès Varhol
2024-01-09 19:41 ` [PATCH v4 1/3] hw/misc: Implement " Inès Varhol
@ 2024-01-09 19:41 ` Inès Varhol
2024-01-11 23:31 ` Alistair Francis
2024-01-09 19:41 ` [PATCH v4 3/3] tests/qtest: Add STM32L4x5 SYSCFG QTest testcase Inès Varhol
2024-01-12 18:13 ` [PATCH v4 0/3] Add device STM32L4x5 SYSCFG Peter Maydell
3 siblings, 1 reply; 6+ messages in thread
From: Inès Varhol @ 2024-01-09 19:41 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Alistair Francis, Samuel Tardieu, Peter Maydell,
qemu-arm, Paolo Bonzini, Arnaud Minier,
Philippe Mathieu-Daudé, Inès Varhol, Laurent Vivier
The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO
device will be implemented, its output GPIOs will be connected to the
SYSCFG input GPIOs.
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 21 ++++++++++++++++++++-
include/hw/arm/stm32l4x5_soc.h | 2 ++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 8c8488a70a..bb4693bfbb 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -459,6 +459,7 @@ config STM32L4X5_SOC
bool
select ARM_V7M
select OR_IRQ
+ select STM32L4X5_SYSCFG
select STM32L4X5_EXTI
config XLNX_ZYNQMP_ARM
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index fe46b7c6c0..431f982caf 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -37,6 +37,7 @@
#define SRAM2_SIZE (32 * KiB)
#define EXTI_ADDR 0x40010400
+#define SYSCFG_ADDR 0x40010000
#define NUM_EXTI_IRQ 40
/* Match exti line connections with their CPU IRQ number */
@@ -80,6 +81,7 @@ static void stm32l4x5_soc_initfn(Object *obj)
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
+ object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
@@ -154,6 +156,19 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ /* System configuration controller */
+ busdev = SYS_BUS_DEVICE(&s->syscfg);
+ if (!sysbus_realize(busdev, errp)) {
+ return;
+ }
+ sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
+ /*
+ * TODO: when the GPIO device is implemented, connect it
+ * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
+ * GPIO_NUM_PINS.
+ */
+
+ /* EXTI device */
busdev = SYS_BUS_DEVICE(&s->exti);
if (!sysbus_realize(busdev, errp)) {
return;
@@ -163,6 +178,11 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
}
+ for (unsigned i = 0; i < 16; i++) {
+ qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
+ qdev_get_gpio_in(DEVICE(&s->exti), i));
+ }
+
/* APB1 BUS */
create_unimplemented_device("TIM2", 0x40000000, 0x400);
create_unimplemented_device("TIM3", 0x40000400, 0x400);
@@ -200,7 +220,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
/* RESERVED: 0x40009800, 0x6800 */
/* APB2 BUS */
- create_unimplemented_device("SYSCFG", 0x40010000, 0x30);
create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0);
create_unimplemented_device("COMP", 0x40010200, 0x200);
/* RESERVED: 0x40010800, 0x1400 */
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
index f7305568dc..baf70410b5 100644
--- a/include/hw/arm/stm32l4x5_soc.h
+++ b/include/hw/arm/stm32l4x5_soc.h
@@ -26,6 +26,7 @@
#include "exec/memory.h"
#include "hw/arm/armv7m.h"
+#include "hw/misc/stm32l4x5_syscfg.h"
#include "hw/misc/stm32l4x5_exti.h"
#include "qom/object.h"
@@ -41,6 +42,7 @@ struct Stm32l4x5SocState {
ARMv7MState armv7m;
Stm32l4x5ExtiState exti;
+ Stm32l4x5SyscfgState syscfg;
MemoryRegion sram1;
MemoryRegion sram2;
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v4 2/3] hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC
2024-01-09 19:41 ` [PATCH v4 2/3] hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC Inès Varhol
@ 2024-01-11 23:31 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2024-01-11 23:31 UTC (permalink / raw)
To: Inès Varhol
Cc: qemu-devel, Thomas Huth, Alistair Francis, Samuel Tardieu,
Peter Maydell, qemu-arm, Paolo Bonzini, Arnaud Minier,
Philippe Mathieu-Daudé, Laurent Vivier
On Wed, Jan 10, 2024 at 5:47 AM Inès Varhol
<ines.varhol@telecom-paris.fr> wrote:
>
> The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO
> device will be implemented, its output GPIOs will be connected to the
> SYSCFG input GPIOs.
>
> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/Kconfig | 1 +
> hw/arm/stm32l4x5_soc.c | 21 ++++++++++++++++++++-
> include/hw/arm/stm32l4x5_soc.h | 2 ++
> 3 files changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 8c8488a70a..bb4693bfbb 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -459,6 +459,7 @@ config STM32L4X5_SOC
> bool
> select ARM_V7M
> select OR_IRQ
> + select STM32L4X5_SYSCFG
> select STM32L4X5_EXTI
>
> config XLNX_ZYNQMP_ARM
> diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
> index fe46b7c6c0..431f982caf 100644
> --- a/hw/arm/stm32l4x5_soc.c
> +++ b/hw/arm/stm32l4x5_soc.c
> @@ -37,6 +37,7 @@
> #define SRAM2_SIZE (32 * KiB)
>
> #define EXTI_ADDR 0x40010400
> +#define SYSCFG_ADDR 0x40010000
>
> #define NUM_EXTI_IRQ 40
> /* Match exti line connections with their CPU IRQ number */
> @@ -80,6 +81,7 @@ static void stm32l4x5_soc_initfn(Object *obj)
> Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
>
> object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
> + object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
>
> s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> @@ -154,6 +156,19 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> return;
> }
>
> + /* System configuration controller */
> + busdev = SYS_BUS_DEVICE(&s->syscfg);
> + if (!sysbus_realize(busdev, errp)) {
> + return;
> + }
> + sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
> + /*
> + * TODO: when the GPIO device is implemented, connect it
> + * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
> + * GPIO_NUM_PINS.
> + */
> +
> + /* EXTI device */
> busdev = SYS_BUS_DEVICE(&s->exti);
> if (!sysbus_realize(busdev, errp)) {
> return;
> @@ -163,6 +178,11 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
> }
>
> + for (unsigned i = 0; i < 16; i++) {
> + qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
> + qdev_get_gpio_in(DEVICE(&s->exti), i));
> + }
> +
> /* APB1 BUS */
> create_unimplemented_device("TIM2", 0x40000000, 0x400);
> create_unimplemented_device("TIM3", 0x40000400, 0x400);
> @@ -200,7 +220,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> /* RESERVED: 0x40009800, 0x6800 */
>
> /* APB2 BUS */
> - create_unimplemented_device("SYSCFG", 0x40010000, 0x30);
> create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0);
> create_unimplemented_device("COMP", 0x40010200, 0x200);
> /* RESERVED: 0x40010800, 0x1400 */
> diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
> index f7305568dc..baf70410b5 100644
> --- a/include/hw/arm/stm32l4x5_soc.h
> +++ b/include/hw/arm/stm32l4x5_soc.h
> @@ -26,6 +26,7 @@
>
> #include "exec/memory.h"
> #include "hw/arm/armv7m.h"
> +#include "hw/misc/stm32l4x5_syscfg.h"
> #include "hw/misc/stm32l4x5_exti.h"
> #include "qom/object.h"
>
> @@ -41,6 +42,7 @@ struct Stm32l4x5SocState {
> ARMv7MState armv7m;
>
> Stm32l4x5ExtiState exti;
> + Stm32l4x5SyscfgState syscfg;
>
> MemoryRegion sram1;
> MemoryRegion sram2;
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 3/3] tests/qtest: Add STM32L4x5 SYSCFG QTest testcase
2024-01-09 19:41 [PATCH v4 0/3] Add device STM32L4x5 SYSCFG Inès Varhol
2024-01-09 19:41 ` [PATCH v4 1/3] hw/misc: Implement " Inès Varhol
2024-01-09 19:41 ` [PATCH v4 2/3] hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC Inès Varhol
@ 2024-01-09 19:41 ` Inès Varhol
2024-01-12 18:13 ` [PATCH v4 0/3] Add device STM32L4x5 SYSCFG Peter Maydell
3 siblings, 0 replies; 6+ messages in thread
From: Inès Varhol @ 2024-01-09 19:41 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Alistair Francis, Samuel Tardieu, Peter Maydell,
qemu-arm, Paolo Bonzini, Arnaud Minier,
Philippe Mathieu-Daudé, Inès Varhol, Laurent Vivier,
Alistair Francis
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4x5_syscfg-test.c | 331 ++++++++++++++++++++++++++++
2 files changed, 333 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/stm32l4x5_syscfg-test.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index d890b6f333..a926af92f6 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -196,7 +196,8 @@ qtests_aspeed = \
'aspeed_gpio-test']
qtests_stm32l4x5 = \
- ['stm32l4x5_exti-test']
+ ['stm32l4x5_exti-test',
+ 'stm32l4x5_syscfg-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
new file mode 100644
index 0000000000..ed4801798d
--- /dev/null
+++ b/tests/qtest/stm32l4x5_syscfg-test.c
@@ -0,0 +1,331 @@
+/*
+ * QTest testcase for STM32L4x5_SYSCFG
+ *
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+#define SYSCFG_BASE_ADDR 0x40010000
+#define SYSCFG_MEMRMP 0x00
+#define SYSCFG_CFGR1 0x04
+#define SYSCFG_EXTICR1 0x08
+#define SYSCFG_EXTICR2 0x0C
+#define SYSCFG_EXTICR3 0x10
+#define SYSCFG_EXTICR4 0x14
+#define SYSCFG_SCSR 0x18
+#define SYSCFG_CFGR2 0x1C
+#define SYSCFG_SWPR 0x20
+#define SYSCFG_SKR 0x24
+#define SYSCFG_SWPR2 0x28
+#define INVALID_ADDR 0x2C
+
+static void syscfg_writel(unsigned int offset, uint32_t value)
+{
+ writel(SYSCFG_BASE_ADDR + offset, value);
+}
+
+static uint32_t syscfg_readl(unsigned int offset)
+{
+ return readl(SYSCFG_BASE_ADDR + offset);
+}
+
+static void syscfg_set_irq(int num, int level)
+{
+ qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
+ NULL, num, level);
+}
+
+static void system_reset(void)
+{
+ QDict *response;
+ response = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
+ g_assert(qdict_haskey(response, "return"));
+ qobject_unref(response);
+}
+
+static void test_reset(void)
+{
+ /*
+ * Test that registers are initialized at the correct values
+ */
+ g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x7C000001);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SCSR), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR2), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x00000000);
+
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR2), ==, 0x00000000);
+}
+
+static void test_reserved_bits(void)
+{
+ /*
+ * Test that reserved bits stay at reset value
+ * (which is 0 for all of them) by writing '1'
+ * in all reserved bits (keeping reset value for
+ * other bits) and checking that the
+ * register is still at reset value
+ */
+ syscfg_writel(SYSCFG_MEMRMP, 0xFFFFFEF8);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_CFGR1, 0x7F00FEFF);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x7C000001);
+
+ syscfg_writel(SYSCFG_EXTICR1, 0xFFFF0000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR2, 0xFFFF0000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR3, 0xFFFF0000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR4, 0xFFFF0000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_SKR, 0xFFFFFF00);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x00000000);
+}
+
+static void test_set_and_clear(void)
+{
+ /*
+ * Test that regular bits can be set and cleared
+ */
+ syscfg_writel(SYSCFG_MEMRMP, 0x00000107);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000107);
+ syscfg_writel(SYSCFG_MEMRMP, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_MEMRMP), ==, 0x00000000);
+
+ /* cfgr1 bit 0 is clear only so we keep it set */
+ syscfg_writel(SYSCFG_CFGR1, 0xFCFF0101);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0xFCFF0101);
+ syscfg_writel(SYSCFG_CFGR1, 0x00000001);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x00000001);
+
+ syscfg_writel(SYSCFG_EXTICR1, 0x0000FFFF);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR1), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR2, 0x0000FFFF);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR2, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR2), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR3, 0x0000FFFF);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR3, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR3), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR4, 0x0000FFFF);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR4, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_EXTICR4), ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_SKR, 0x000000FF);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x000000FF);
+ syscfg_writel(SYSCFG_SKR, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SKR), ==, 0x00000000);
+}
+
+static void test_clear_by_writing_1(void)
+{
+ /*
+ * Test that writing '1' doesn't set the bit
+ */
+ syscfg_writel(SYSCFG_CFGR2, 0x00000100);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR2), ==, 0x00000000);
+}
+
+static void test_set_only_bits(void)
+{
+ /*
+ * Test that set only bits stay can't be cleared
+ */
+ syscfg_writel(SYSCFG_CFGR2, 0x0000000F);
+ syscfg_writel(SYSCFG_CFGR2, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR2), ==, 0x0000000F);
+
+ syscfg_writel(SYSCFG_SWPR, 0xFFFFFFFF);
+ syscfg_writel(SYSCFG_SWPR, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR), ==, 0xFFFFFFFF);
+
+ syscfg_writel(SYSCFG_SWPR2, 0xFFFFFFFF);
+ syscfg_writel(SYSCFG_SWPR2, 0x00000000);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_SWPR2), ==, 0xFFFFFFFF);
+
+ system_reset();
+}
+
+static void test_clear_only_bits(void)
+{
+ /*
+ * Test that clear only bits stay can't be set
+ */
+ syscfg_writel(SYSCFG_CFGR1, 0x00000000);
+ syscfg_writel(SYSCFG_CFGR1, 0x00000001);
+ g_assert_cmpuint(syscfg_readl(SYSCFG_CFGR1), ==, 0x00000000);
+
+ system_reset();
+}
+
+static void test_interrupt(void)
+{
+ /*
+ * Test that GPIO rising lines result in an irq
+ * with the right configuration
+ */
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+
+ /* GPIOA is the default source for EXTI lines 0 to 15 */
+
+ syscfg_set_irq(0, 1);
+
+ g_assert_true(get_irq(0));
+
+
+ syscfg_set_irq(15, 1);
+
+ g_assert_true(get_irq(15));
+
+ /* Configure GPIOB[1] as the source input for EXTI1 */
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000010);
+
+ syscfg_set_irq(17, 1);
+
+ g_assert_true(get_irq(1));
+
+ /* Clean the test */
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
+ syscfg_set_irq(0, 0);
+ syscfg_set_irq(15, 0);
+ syscfg_set_irq(17, 0);
+}
+
+static void test_irq_pin_multiplexer(void)
+{
+ /*
+ * Test that syscfg irq sets the right exti irq
+ */
+
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+
+ syscfg_set_irq(0, 1);
+
+ /* Check that irq 0 was set and irq 15 wasn't */
+ g_assert_true(get_irq(0));
+ g_assert_false(get_irq(15));
+
+ /* Clean the test */
+ syscfg_set_irq(0, 0);
+
+ syscfg_set_irq(15, 1);
+
+ /* Check that irq 15 was set and irq 0 wasn't */
+ g_assert_true(get_irq(15));
+ g_assert_false(get_irq(0));
+
+ /* Clean the test */
+ syscfg_set_irq(15, 0);
+}
+
+static void test_irq_gpio_multiplexer(void)
+{
+ /*
+ * Test that an irq is generated only by the right GPIO
+ */
+
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+
+ /* GPIOA is the default source for EXTI lines 0 to 15 */
+
+ /* Check that setting rising pin GPIOA[0] generates an irq */
+ syscfg_set_irq(0, 1);
+
+ g_assert_true(get_irq(0));
+
+ /* Clean the test */
+ syscfg_set_irq(0, 0);
+
+ /* Check that setting rising pin GPIOB[0] doesn't generate an irq */
+ syscfg_set_irq(16, 1);
+
+ g_assert_false(get_irq(0));
+
+ /* Clean the test */
+ syscfg_set_irq(16, 0);
+
+ /* Configure GPIOB[0] as the source input for EXTI0 */
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000001);
+
+ /* Check that setting rising pin GPIOA[0] doesn't generate an irq */
+ syscfg_set_irq(0, 1);
+
+ g_assert_false(get_irq(0));
+
+ /* Clean the test */
+ syscfg_set_irq(0, 0);
+
+ /* Check that setting rising pin GPIOB[0] generates an irq */
+ syscfg_set_irq(16, 1);
+
+ g_assert_true(get_irq(0));
+
+ /* Clean the test */
+ syscfg_set_irq(16, 0);
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+ g_test_set_nonfatal_assertions();
+
+ qtest_add_func("stm32l4x5/syscfg/test_reset", test_reset);
+ qtest_add_func("stm32l4x5/syscfg/test_reserved_bits",
+ test_reserved_bits);
+ qtest_add_func("stm32l4x5/syscfg/test_set_and_clear",
+ test_set_and_clear);
+ qtest_add_func("stm32l4x5/syscfg/test_clear_by_writing_1",
+ test_clear_by_writing_1);
+ qtest_add_func("stm32l4x5/syscfg/test_set_only_bits",
+ test_set_only_bits);
+ qtest_add_func("stm32l4x5/syscfg/test_clear_only_bits",
+ test_clear_only_bits);
+ qtest_add_func("stm32l4x5/syscfg/test_interrupt",
+ test_interrupt);
+ qtest_add_func("stm32l4x5/syscfg/test_irq_pin_multiplexer",
+ test_irq_pin_multiplexer);
+ qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer",
+ test_irq_gpio_multiplexer);
+
+ qtest_start("-machine b-l475e-iot01a");
+ ret = g_test_run();
+ qtest_end();
+
+ return ret;
+}
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v4 0/3] Add device STM32L4x5 SYSCFG
2024-01-09 19:41 [PATCH v4 0/3] Add device STM32L4x5 SYSCFG Inès Varhol
` (2 preceding siblings ...)
2024-01-09 19:41 ` [PATCH v4 3/3] tests/qtest: Add STM32L4x5 SYSCFG QTest testcase Inès Varhol
@ 2024-01-12 18:13 ` Peter Maydell
3 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2024-01-12 18:13 UTC (permalink / raw)
To: Inès Varhol
Cc: qemu-devel, Thomas Huth, Alistair Francis, Samuel Tardieu,
qemu-arm, Paolo Bonzini, Arnaud Minier,
Philippe Mathieu-Daudé, Laurent Vivier
On Tue, 9 Jan 2024 at 19:44, Inès Varhol <ines.varhol@telecom-paris.fr> wrote:
>
> This patch adds a new device STM32L4x5 SYSCFG device and is part
> of a series implementing the STM32L4x5 with a few peripherals.
>
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread