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Wed, 25 Mar 2026 19:28:37 -0700 (PDT) MIME-Version: 1.0 References: <20260318103122.97244-1-philmd@linaro.org> In-Reply-To: <20260318103122.97244-1-philmd@linaro.org> From: Alistair Francis Date: Thu, 26 Mar 2026 12:28:09 +1000 X-Gm-Features: AQROBzBqeSrnkg-dvUZZsDZAnVYn5Gyj1rh3nPBNEqi5i-hKQdsRSM6ADReBkA0 Message-ID: Subject: Re: [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Weiwei Li , Pierrick Bouvier , Warner Losh , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , Vijai Kumar K , Anton Johansson , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Jiaxun Yang , Peter Maydell , Liu Zhiwei , Djordje Todorovic Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 18, 2026 at 8:33=E2=80=AFPM Philippe Mathieu-Daud=C3=A9 wrote: > > Thanks to Fr=C3=A9d=C3=A9ric patch on 128-bit registers, we can now > remove all legacy native endianness API uses of RISC-V. > > Djordje: You should (re)base your "Add RISC-V big-endian > target support" [*] series on this (after addressing the > review comments) before posting your v4. > > [*] https://lore.kernel.org/qemu-devel/20260311115910.564481-1-djordje.to= dorovic@htecgroup.com/ > > Djordje Todorovic (1): > target/riscv: Use MO_LE for instruction fetch > > Fr=C3=A9d=C3=A9ric P=C3=A9trot (2): > target/riscv: Make LQ and SQ use 128-bit ld/st > target/riscv: Remove MTTCG check for x-rv128 CPU model > > Philippe Mathieu-Daud=C3=A9 (13): > hw/riscv: Mark RISC-V specific peripherals as little-endian > target/riscv: Use explicit little-endian LD/ST API > target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) > target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / > store_release > target/riscv: Factor tiny ldn() helper in gdbstub > target/riscv: Simplify riscv_cpu_gdb_write_register() > target/riscv: Expose mo_endian_env() > target/riscv: Have gdbstub consider CPU endianness > target/riscv: Replace MO_TE by mo_endian (MIPS extension) > target/riscv: Replace MO_TE by mo_endian (Zilsd extension) > target/riscv: Replace MO_TE by mo_endian (Zalasr extension) > target/riscv: Replace MO_TE -> MO_LE > configs/targets: Forbid RISC-V to use legacy native endianness APIs Thanks! Applied to riscv-to-apply.next Alistair > > configs/targets/riscv32-linux-user.mak | 1 + > configs/targets/riscv32-softmmu.mak | 1 + > configs/targets/riscv64-bsd-user.mak | 1 + > configs/targets/riscv64-linux-user.mak | 1 + > configs/targets/riscv64-softmmu.mak | 1 + > target/riscv/internals.h | 12 ++++++ > hw/char/ibex_uart.c | 2 +- > hw/char/shakti_uart.c | 2 +- > hw/char/sifive_uart.c | 2 +- > hw/misc/sifive_e_aon.c | 2 +- > hw/misc/sifive_e_prci.c | 2 +- > hw/misc/sifive_u_otp.c | 2 +- > hw/misc/sifive_u_prci.c | 2 +- > hw/riscv/riscv-iommu.c | 2 +- > hw/sd/cadence_sdhci.c | 2 +- > hw/timer/ibex_timer.c | 2 +- > hw/timer/sifive_pwm.c | 2 +- > target/riscv/cpu_helper.c | 4 +- > target/riscv/gdbstub.c | 42 ++++++++------------ > target/riscv/op_helper.c | 14 ------- > target/riscv/tcg/tcg-cpu.c | 10 ----- > target/riscv/translate.c | 10 ++--- > target/riscv/insn_trans/trans_rvi.c.inc | 32 +++++++++++---- > target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 +++++---- > target/riscv/insn_trans/trans_xmips.c.inc | 24 +++++++---- > target/riscv/insn_trans/trans_zilsd.c.inc | 4 +- > 26 files changed, 104 insertions(+), 93 deletions(-) > > -- > 2.53.0 > >