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Tue, 03 Dec 2024 18:36:44 -0800 (PST) MIME-Version: 1.0 References: <20241203034932.25185-1-fea.wang@sifive.com> In-Reply-To: <20241203034932.25185-1-fea.wang@sifive.com> From: Alistair Francis Date: Wed, 4 Dec 2024 11:36:18 +0900 Message-ID: Subject: Re: [PATCH v5 0/6] Introduce svukte ISA extension To: "Fea.Wang" Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a30; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Dec 3, 2024 at 12:39=E2=80=AFPM Fea.Wang wrot= e: > > The Svukte ISA extension has been approved for fast-track development. > https://lf-riscv.atlassian.net/browse/RVS-2977 > And there are Linux patches for the Svukte that are under review. > https://lore.kernel.org/kvm/20240920-dev-maxh-svukte-rebase-v1-0-7864a88a= 62bd@sifive.com/T/#mf70fcb22cd2987ad268c0efee9b8583197d3cb4f > > Svukte provides a means to make user-mode accesses to supervisor memory > raise page faults in constant time, mitigating attacks that attempt to > discover the supervisor software's address-space layout. > > Refer to the draft of svukte extension from: > https://github.com/riscv/riscv-isa-manual/pull/1564 > > base-commit: 2209cae121e5da3cfbdb9dd4b06d52d0ef66ea69 > > [v5] > * Update the warning log and the commit message > > [v4] > * Add a svukte extension check in RV32. > * Refine the code. > > [v3] > * Fix some typos > * Refine code by separating a function into two dedicated functions. > * Follow the riscv,isa order > > [v2] > * Refactor the code > > [v1] > * Add svukte extension > > Fea.Wang (6): > target/riscv: Add svukte extension capability variable > target/riscv: Support senvcfg[UKTE] bit when svukte extension is > enabled > target/riscv: Support hstatus[HUKTE] bit when svukte extension is > enabled > target/riscv: Check memory access to meet svukte rule > target/riscv: Expose svukte ISA extension > target/riscv: Check svukte is not enabled in RV32 Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_bits.h | 2 ++ > target/riscv/cpu_cfg.h | 1 + > target/riscv/cpu_helper.c | 55 ++++++++++++++++++++++++++++++++++++++ > target/riscv/csr.c | 7 +++++ > target/riscv/tcg/tcg-cpu.c | 5 ++++ > 6 files changed, 72 insertions(+) > > -- > 2.34.1 > >