From: Alistair Francis <alistair23@gmail.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
alistair.francis@wdc.com
Subject: Re: [PATCH v2 0/2] Minor mhpmevent related fixes
Date: Mon, 10 Feb 2025 12:54:57 +1000 [thread overview]
Message-ID: <CAKmqyKMuNS6kAytheSAwDXo1MEOvadi-0nXMOR9BRN_hKRnYEw@mail.gmail.com> (raw)
In-Reply-To: <20250206-pmu_minor_fixes-v2-0-1bb0f4aeb8b4@rivosinc.com>
On Thu, Feb 6, 2025 at 7:59 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> Here are two small fixes around mhpmevent encoding and reset value.
> The first patch is picked from the platform specific event encoding
> series[1].
>
> [1] https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com/
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Changes in v2:
> - Replace GENMASK_ULL with MAKE_64BIT_MASK
> - Applied RB/AB tags.
> - Link to v1: https://lore.kernel.org/r/20250115-pmu_minor_fixes-v1-0-c32388defb02@rivosinc.com
>
> ---
> Atish Patra (2):
> target/riscv: Fix the hpmevent mask
> target/riscv: Mask out upper sscofpmf bits during validation
>
> target/riscv/cpu_bits.h | 5 ++---
> target/riscv/pmu.c | 2 +-
> 2 files changed, 3 insertions(+), 4 deletions(-)
> ---
> base-commit: 3f26a7a370c11c7dff68dabcccc19c4e0de901e4
> change-id: 20250115-pmu_minor_fixes-7a2b8e3658e4
> --
> Regards,
> Atish patra
>
>
prev parent reply other threads:[~2025-02-10 2:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 9:58 [PATCH v2 0/2] Minor mhpmevent related fixes Atish Patra
2025-02-06 9:58 ` [PATCH v2 1/2] target/riscv: Fix the hpmevent mask Atish Patra
2025-02-10 1:22 ` Alistair Francis
2025-02-06 9:58 ` [PATCH v2 2/2] target/riscv: Mask out upper sscofpmf bits during validation Atish Patra
2025-02-10 2:54 ` Alistair Francis [this message]
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