[PATCH v2 0/2] Minor mhpmevent related fixes

[PATCH v2 0/2] Minor mhpmevent related fixes

[Atish Patra]

Here are two small fixes around mhpmevent encoding and reset value.
The first patch is picked from the platform specific event encoding
series[1].

[1] https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com/

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
Changes in v2:
- Replace GENMASK_ULL with MAKE_64BIT_MASK
- Applied RB/AB tags.
- Link to v1: https://lore.kernel.org/r/20250115-pmu_minor_fixes-v1-0-c32388defb02@rivosinc.com

---
Atish Patra (2):
      target/riscv: Fix the hpmevent mask
      target/riscv: Mask out upper sscofpmf bits during validation

 target/riscv/cpu_bits.h | 5 ++---
 target/riscv/pmu.c      | 2 +-
 2 files changed, 3 insertions(+), 4 deletions(-)
---
base-commit: 3f26a7a370c11c7dff68dabcccc19c4e0de901e4
change-id: 20250115-pmu_minor_fixes-7a2b8e3658e4
--
Regards,
Atish patra

[PATCH v2 1/2] target/riscv: Fix the hpmevent mask

[Atish Patra]

As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.

[1]https://github.com/riscv/riscv-isa-manual/issues/1578

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/cpu_bits.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f97c48a3943f..74859c4bc8ff 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -933,9 +933,8 @@ typedef enum RISCVException {
                                             MHPMEVENTH_BIT_VSINH | \
                                             MHPMEVENTH_BIT_VUINH)
 
-#define MHPMEVENT_SSCOF_MASK               _ULL(0xFFFF000000000000)
-#define MHPMEVENT_IDX_MASK                 0xFFFFF
-#define MHPMEVENT_SSCOF_RESVD              16
+#define MHPMEVENT_SSCOF_MASK               MAKE_64BIT_MASK(63, 56)
+#define MHPMEVENT_IDX_MASK                 (~MHPMEVENT_SSCOF_MASK)
 
 /* RISC-V-specific interrupt pending bits. */
 #define CPU_INTERRUPT_RNMI                 CPU_INTERRUPT_TGT_EXT_0

-- 
2.43.0

Re: [PATCH v2 1/2] target/riscv: Fix the hpmevent mask

[Alistair Francis]

On Thu, Feb 6, 2025 at 7:59 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> As per the latest privilege specification v1.13[1], the sscofpmf
> only reserves first 8 bits of hpmeventX. Update the corresponding
> masks accordingly.
>
> [1]https://github.com/riscv/riscv-isa-manual/issues/1578
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_bits.h | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f97c48a3943f..74859c4bc8ff 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -933,9 +933,8 @@ typedef enum RISCVException {
>                                              MHPMEVENTH_BIT_VSINH | \
>                                              MHPMEVENTH_BIT_VUINH)
>
> -#define MHPMEVENT_SSCOF_MASK               _ULL(0xFFFF000000000000)
> -#define MHPMEVENT_IDX_MASK                 0xFFFFF
> -#define MHPMEVENT_SSCOF_RESVD              16
> +#define MHPMEVENT_SSCOF_MASK               MAKE_64BIT_MASK(63, 56)
> +#define MHPMEVENT_IDX_MASK                 (~MHPMEVENT_SSCOF_MASK)
>
>  /* RISC-V-specific interrupt pending bits. */
>  #define CPU_INTERRUPT_RNMI                 CPU_INTERRUPT_TGT_EXT_0
>
> --
> 2.43.0
>
>

[PATCH v2 2/2] target/riscv: Mask out upper sscofpmf bits during validation

[Atish Patra]

As per the ISA definition, the upper 8 bits in hpmevent are defined
by Sscofpmf for privilege mode filtering and overflow bits while the
lower 56 bits are desginated for platform specific hpmevent values.
For the reset case, mhpmevent value should have zero in lower 56 bits.
Software may set the OF bit to indicate disable interrupt.

Ensure that correct value is checked after masking while clearing the
event encodings.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index cf713663ee56..0408f96e6af8 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -390,7 +390,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
      * Expected mhpmevent value is zero for reset case. Remove the current
      * mapping.
      */
-    if (!value) {
+    if (!(value & MHPMEVENT_IDX_MASK)) {
         g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
                                     pmu_remove_event_map,
                                     GUINT_TO_POINTER(ctr_idx));

-- 
2.43.0

Re: [PATCH v2 0/2] Minor mhpmevent related fixes

[Alistair Francis]

On Thu, Feb 6, 2025 at 7:59 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> Here are two small fixes around mhpmevent encoding and reset value.
> The first patch is picked from the platform specific event encoding
> series[1].
>
> [1] https://lore.kernel.org/qemu-devel/20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com/
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
> Changes in v2:
> - Replace GENMASK_ULL with MAKE_64BIT_MASK
> - Applied RB/AB tags.
> - Link to v1: https://lore.kernel.org/r/20250115-pmu_minor_fixes-v1-0-c32388defb02@rivosinc.com
>
> ---
> Atish Patra (2):
>       target/riscv: Fix the hpmevent mask
>       target/riscv: Mask out upper sscofpmf bits during validation
>
>  target/riscv/cpu_bits.h | 5 ++---
>  target/riscv/pmu.c      | 2 +-
>  2 files changed, 3 insertions(+), 4 deletions(-)
> ---
> base-commit: 3f26a7a370c11c7dff68dabcccc19c4e0de901e4
> change-id: 20250115-pmu_minor_fixes-7a2b8e3658e4
> --
> Regards,
> Atish patra
>
>