From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36505) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eHfSP-00009E-AD for qemu-devel@nongnu.org; Wed, 22 Nov 2017 19:33:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eHfSO-0005Wn-CE for qemu-devel@nongnu.org; Wed, 22 Nov 2017 19:33:33 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:44628) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eHfSO-0005WX-6Z for qemu-devel@nongnu.org; Wed, 22 Nov 2017 19:33:32 -0500 Received: by mail-wm0-x242.google.com with SMTP id r68so13689952wmr.3 for ; Wed, 22 Nov 2017 16:33:32 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <20171103000109.28244-6-frasse.iglesias@gmail.com> References: <20171103000109.28244-1-frasse.iglesias@gmail.com> <20171103000109.28244-6-frasse.iglesias@gmail.com> From: Alistair Francis Date: Wed, 22 Nov 2017 16:33:00 -0800 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH v7 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Francisco Iglesias Cc: "qemu-devel@nongnu.org Developers" , Peter Maydell , Edgar Iglesias , Alistair Francis , francisco.iglesias@feimtech.se, "mar.krzeminski" On Thu, Nov 2, 2017 at 5:01 PM, Francisco Iglesias wrote: > Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the > header for consistency (struct XilinxSPIPS is found there). Also move out > a define and remove two dubbel included headers (while touching the code). s/dubbel/double/g > Finally, add 4 byte address commands to the FlashCMD enum. This probably could be a separate patch, but I'm not fussed either way. > > Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Alistair > --- > hw/ssi/xilinx_spips.c | 35 ----------------------------------- > include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ > 2 files changed, 34 insertions(+), 35 deletions(-) > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index ef56d35..559fa79 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -27,8 +27,6 @@ > #include "sysemu/sysemu.h" > #include "hw/ptimer.h" > #include "qemu/log.h" > -#include "qemu/fifo8.h" > -#include "hw/ssi/ssi.h" > #include "qemu/bitops.h" > #include "hw/ssi/xilinx_spips.h" > #include "qapi/error.h" > @@ -116,44 +114,11 @@ > > /* 16MB per linear region */ > #define LQSPI_ADDRESS_BITS 24 > -/* Bite off 4k chunks at a time */ > -#define LQSPI_CACHE_SIZE 1024 > > #define SNOOP_CHECKING 0xFF > #define SNOOP_NONE 0xFE > #define SNOOP_STRIPING 0 > > -typedef enum { > - READ = 0x3, > - FAST_READ = 0xb, > - DOR = 0x3b, > - QOR = 0x6b, > - DIOR = 0xbb, > - QIOR = 0xeb, > - > - PP = 0x2, > - DPP = 0xa2, > - QPP = 0x32, > -} FlashCMD; > - > -typedef struct { > - XilinxSPIPS parent_obj; > - > - uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; > - hwaddr lqspi_cached_addr; > - Error *migration_blocker; > - bool mmio_execution_enabled; > -} XilinxQSPIPS; > - > -typedef struct XilinxSPIPSClass { > - SysBusDeviceClass parent_class; > - > - const MemoryRegionOps *reg_ops; > - > - uint32_t rx_fifo_size; > - uint32_t tx_fifo_size; > -} XilinxSPIPSClass; > - > static inline int num_effective_busses(XilinxSPIPS *s) > { > return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && > diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h > index 06aa096..7f9e2fc 100644 > --- a/include/hw/ssi/xilinx_spips.h > +++ b/include/hw/ssi/xilinx_spips.h > @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; > > #define XLNX_SPIPS_R_MAX (0x100 / 4) > > +/* Bite off 4k chunks at a time */ > +#define LQSPI_CACHE_SIZE 1024 > + > +typedef enum { > + READ = 0x3, READ_4 = 0x13, > + FAST_READ = 0xb, FAST_READ_4 = 0x0c, > + DOR = 0x3b, DOR_4 = 0x3c, > + QOR = 0x6b, QOR_4 = 0x6c, > + DIOR = 0xbb, DIOR_4 = 0xbc, > + QIOR = 0xeb, QIOR_4 = 0xec, > + > + PP = 0x2, PP_4 = 0x12, > + DPP = 0xa2, > + QPP = 0x32, QPP_4 = 0x34, > +} FlashCMD; > + > struct XilinxSPIPS { > SysBusDevice parent_obj; > > @@ -56,6 +72,24 @@ struct XilinxSPIPS { > uint32_t regs[XLNX_SPIPS_R_MAX]; > }; > > +typedef struct { > + XilinxSPIPS parent_obj; > + > + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; > + hwaddr lqspi_cached_addr; > + Error *migration_blocker; > + bool mmio_execution_enabled; > +} XilinxQSPIPS; > + > +typedef struct XilinxSPIPSClass { > + SysBusDeviceClass parent_class; > + > + const MemoryRegionOps *reg_ops; > + > + uint32_t rx_fifo_size; > + uint32_t tx_fifo_size; > +} XilinxSPIPSClass; > + > #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" > #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" > > -- > 2.9.3 > >