qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH 2/8] target/riscv: make CPUCFG() macro public
Date: Thu, 10 Aug 2023 13:31:28 -0400	[thread overview]
Message-ID: <CAKmqyKMw2=Qbcvr-osegDxiodg+EDYaCJ-_QSeSaS8g6Mbp7Qw@mail.gmail.com> (raw)
In-Reply-To: <20230728131520.110394-3-dbarboza@ventanamicro.com>

On Fri, Jul 28, 2023 at 9:20 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
> of a certain field in the struct RISCVCPUConfig. We're going to use this
> macro in target/riscv/cpu.c as well in the next patches. Make it public.
>
> Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 2 +-
>  target/riscv/cpu.h | 2 ++
>  target/riscv/kvm.c | 8 +++-----
>  3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 644ce7a018..3e62881d85 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -48,7 +48,7 @@ struct isa_ext_data {
>  };
>
>  #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
> -    {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
> +    {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
>
>  /*
>   * From vector_helper.c
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6ea22e0eea..577abcd724 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -62,6 +62,8 @@
>  const char *riscv_get_misa_ext_name(uint32_t bit);
>  const char *riscv_get_misa_ext_description(uint32_t bit);
>
> +#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
> +
>  /* Privileged specification version */
>  enum {
>      PRIV_VERSION_1_10_0 = 0,
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 9d8a8982f9..9b8565d809 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -198,10 +198,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
>      }
>  }
>
> -#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
> -
>  #define KVM_EXT_CFG(_name, _prop, _reg_id) \
> -    {.name = _name, .offset = CPUCFG(_prop), \
> +    {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
>       .kvm_reg_id = _reg_id}
>
>  static KVMCPUConfig kvm_multi_ext_cfgs[] = {
> @@ -278,13 +276,13 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v,
>
>  static KVMCPUConfig kvm_cbom_blocksize = {
>      .name = "cbom_blocksize",
> -    .offset = CPUCFG(cbom_blocksize),
> +    .offset = CPU_CFG_OFFSET(cbom_blocksize),
>      .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)
>  };
>
>  static KVMCPUConfig kvm_cboz_blocksize = {
>      .name = "cboz_blocksize",
> -    .offset = CPUCFG(cboz_blocksize),
> +    .offset = CPU_CFG_OFFSET(cboz_blocksize),
>      .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
>  };
>
> --
> 2.41.0
>
>


  reply	other threads:[~2023-08-10 17:32 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-28 13:15 [PATCH 0/8] riscv: detecting user choice in TCG extensions Daniel Henrique Barboza
2023-07-28 13:15 ` [PATCH 1/8] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Daniel Henrique Barboza
2023-08-10 17:30   ` Alistair Francis
2023-07-28 13:15 ` [PATCH 2/8] target/riscv: make CPUCFG() macro public Daniel Henrique Barboza
2023-08-10 17:31   ` Alistair Francis [this message]
2023-07-28 13:15 ` [PATCH 3/8] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-08-11 14:50   ` Alistair Francis
2023-07-28 13:15 ` [PATCH 4/8] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Daniel Henrique Barboza
2023-08-11 14:52   ` Alistair Francis
2023-07-28 13:15 ` [PATCH 5/8] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Daniel Henrique Barboza
2023-08-11 15:03   ` Alistair Francis
2023-07-28 13:15 ` [PATCH 6/8] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Daniel Henrique Barboza
2023-08-11 15:04   ` Alistair Francis
2023-07-28 13:15 ` [PATCH 7/8] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-08-11 15:04   ` Alistair Francis
2023-07-28 13:15 ` [PATCH 8/8] target/riscv/cpu.c: consider user option with RVG Daniel Henrique Barboza
2023-08-11 15:05   ` Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAKmqyKMw2=Qbcvr-osegDxiodg+EDYaCJ-_QSeSaS8g6Mbp7Qw@mail.gmail.com' \
    --to=alistair23@gmail.com \
    --cc=alistair.francis@wdc.com \
    --cc=bmeng@tinylab.org \
    --cc=dbarboza@ventanamicro.com \
    --cc=liweiwei@iscas.ac.cn \
    --cc=palmer@rivosinc.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).