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Wed, 14 May 2025 22:30:34 -0700 (PDT) MIME-Version: 1.0 References: <20250512095226.93621-1-pbonzini@redhat.com> <20250512095226.93621-15-pbonzini@redhat.com> In-Reply-To: <20250512095226.93621-15-pbonzini@redhat.com> From: Alistair Francis Date: Thu, 15 May 2025 15:30:08 +1000 X-Gm-Features: AX0GCFsHmX1wetSmWbzRfB9CxBSuzhgoEliLpfey7n1-0_bxpXXLIGWlworwXSk Message-ID: Subject: Re: [PATCH 14/26] target/riscv: convert bare CPU models to RISCVCPUDef To: Paolo Bonzini Cc: qemu-devel@nongnu.org, dbarboza@ventanamicro.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2c; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, May 12, 2025 at 7:53=E2=80=AFPM Paolo Bonzini = wrote: > > Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 58 ++++++++++++++-------------------------------- > 1 file changed, 17 insertions(+), 41 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 06c612afba7..af5b4af4814 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -732,18 +732,6 @@ static void rv128_base_cpu_init(Object *obj) > } > #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ > > -static void rv64i_bare_cpu_init(Object *obj) > -{ > - CPURISCVState *env =3D &RISCV_CPU(obj)->env; > - riscv_cpu_set_misa_ext(env, RVI); > -} > - > -static void rv64e_bare_cpu_init(Object *obj) > -{ > - CPURISCVState *env =3D &RISCV_CPU(obj)->env; > - riscv_cpu_set_misa_ext(env, RVE); > -} > - > #endif /* !TARGET_RISCV64 */ > > #if defined(TARGET_RISCV32) || \ > @@ -836,18 +824,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > cpu->cfg.ext_zicsr =3D true; > cpu->cfg.pmp =3D true; > } > - > -static void rv32i_bare_cpu_init(Object *obj) > -{ > - CPURISCVState *env =3D &RISCV_CPU(obj)->env; > - riscv_cpu_set_misa_ext(env, RVI); > -} > - > -static void rv32e_bare_cpu_init(Object *obj) > -{ > - CPURISCVState *env =3D &RISCV_CPU(obj)->env; > - riscv_cpu_set_misa_ext(env, RVE); > -} > #endif > > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > @@ -3216,19 +3192,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt,= char *nodename) > }), \ > } > > -#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \ > - { \ > - .name =3D (type_name), \ > - .parent =3D TYPE_RISCV_BARE_CPU, \ > - .instance_init =3D (initfn), \ > - .class_data =3D &(const RISCVCPUDef) { \ > - .misa_mxl_max =3D (misa_mxl_max_), \ > - .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ > - .vext_spec =3D RISCV_PROFILE_ATTR_UNUSED, \ > - .cfg.max_satp_mode =3D -1, \ > - }, \ > - } > - > #define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \ > { \ > .name =3D (type_name), \ > @@ -3313,8 +3276,15 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_= e_cpu_init), > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_= nommu_cpu_init), > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_= u_cpu_init), > - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_c= pu_init), > - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_c= pu_init), > + > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32I, TYPE_RISCV_BARE_CPU, > + .misa_mxl_max =3D MXL_RV32, > + .misa_ext =3D RVI > + ), > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV32E, TYPE_RISCV_BARE_CPU, > + .misa_mxl_max =3D MXL_RV32, > + .misa_ext =3D RVE > + ), > #endif > > #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY)) > @@ -3334,8 +3304,14 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { > #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_c= pu_init), > #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ > - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_c= pu_init), > - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_c= pu_init), > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64I, TYPE_RISCV_BARE_CPU, > + .misa_mxl_max =3D MXL_RV64, > + .misa_ext =3D RVI > + ), > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RV64E, TYPE_RISCV_BARE_CPU, > + .misa_mxl_max =3D MXL_RV64, > + .misa_ext =3D RVE > + ), > > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, TYPE_RISCV_CPU_RV64I, = RVA22U64), > DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, TYPE_RISCV_CPU_RV64I, = RVA22S64), > -- > 2.49.0 >