From: Alistair Francis <alistair23@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v1 1/1] MAINTAINERS: Add a SiFIve machine section
Date: Wed, 10 Feb 2021 14:32:50 -0800 [thread overview]
Message-ID: <CAKmqyKN1_WTzaoYoAHgxy4RALdLPeA6ZMcbO5PkBy_u5O-mLBg@mail.gmail.com> (raw)
In-Reply-To: <6bc077e5ae4a9512c8adf81ae194718f2f17c402.1612836645.git.alistair.francis@wdc.com>
On Mon, Feb 8, 2021 at 6:11 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Acked-by: Bin Meng <bin.meng@windriver.com>
Thanks!
Applied to riscv-to-apply.next with the title fixed.
Alistair
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8d8b0bf966..c347d49bd2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1359,6 +1359,15 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
> F: include/hw/misc/mchp_pfsoc_ioscb.h
> F: include/hw/misc/mchp_pfsoc_sysreg.h
>
> +SiFive Machines
> +M: Alistair Francis <Alistair.Francis@wdc.com>
> +M: Bin Meng <bin.meng@windriver.com>
> +M: Palmer Dabbelt <palmer@dabbelt.com>
> +L: qemu-riscv@nongnu.org
> +S: Supported
> +F: hw/*/*sifive*.c
> +F: include/hw/*/*sifive*.h
> +
> RX Machines
> -----------
> rx-gdbsim
> --
> 2.30.0
>
prev parent reply other threads:[~2021-02-10 22:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-09 2:11 [PATCH v1 1/1] MAINTAINERS: Add a SiFIve machine section Alistair Francis
2021-02-09 2:14 ` Bin Meng
2021-02-09 9:03 ` Philippe Mathieu-Daudé
2021-02-09 2:17 ` Palmer Dabbelt
2021-02-10 22:32 ` Alistair Francis [this message]
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