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Sun, 08 Mar 2026 21:55:32 -0700 (PDT) MIME-Version: 1.0 References: <20260306071105.3328365-1-max.chou@sifive.com> <20260306071105.3328365-4-max.chou@sifive.com> In-Reply-To: <20260306071105.3328365-4-max.chou@sifive.com> From: Alistair Francis Date: Mon, 9 Mar 2026 14:55:06 +1000 X-Gm-Features: AaiRm52p3kL1LnsPLIsPUHVM7AaFNSSWKz0wSqL2ECu7qMdSCObxsNWK9tskDt0 Message-ID: Subject: Re: [PATCH v5 3/9] target/riscv: rvv: Add new VTYPE CSR field - altfmt To: Max Chou Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Daniel Henrique Barboza Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Mar 6, 2026 at 5:13=E2=80=AFPM Max Chou wrote= : > > According to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field: > altfmt for BF16 support. > This update changes the layout of the vtype CSR fields. > > - Removed VEDIV field (bits 8-9) since EDIV extension is not planned to > be part of the base V extension > - Added ALTFMT field at bit 8 > - Changed RESERVED field to start from bit 9 instead of bit 10 > > When Zvfbfa is disabled, bits 8+ are treated as reserved (preserving > existing behavior for altfmt bit). When Zvfbfa is enabled, only bits 9+ > are reserved. > > Reference: > - https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc > > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Chao Liu > Signed-off-by: Max Chou Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h | 4 ++-- > target/riscv/vector_helper.c | 39 +++++++++++++++++++++++++++++++----- > 2 files changed, 36 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 35d1f6362c..962cc45073 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -191,8 +191,8 @@ FIELD(VTYPE, VLMUL, 0, 3) > FIELD(VTYPE, VSEW, 3, 3) > FIELD(VTYPE, VTA, 6, 1) > FIELD(VTYPE, VMA, 7, 1) > -FIELD(VTYPE, VEDIV, 8, 2) > -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) > +FIELD(VTYPE, ALTFMT, 8, 1) > +FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10) > > typedef struct PMUCTRState { > /* Current value of a counter */ > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index caa8dd9c12..7575e24084 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -33,6 +33,22 @@ > #include "vector_internals.h" > #include > > +static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtyp= e) > +{ > + int xlen =3D riscv_cpu_xlen(env); > + target_ulong reserved =3D 0; > + > + if (riscv_cpu_cfg(env)->ext_zvfbfa) { > + reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, > + xlen - 1 - R_VTYPE_RESERVED_S= HIFT); > + } else { > + reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT, > + xlen - 1 - R_VTYPE_ALTFMT_SHI= FT); > + } > + > + return reserved; > +} > + > target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > target_ulong s2, target_ulong x0) > { > @@ -41,12 +57,10 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, targe= t_ulong s1, > uint64_t vlmul =3D FIELD_EX64(s2, VTYPE, VLMUL); > uint8_t vsew =3D FIELD_EX64(s2, VTYPE, VSEW); > uint16_t sew =3D 8 << vsew; > - uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); > + uint8_t altfmt =3D FIELD_EX64(s2, VTYPE, ALTFMT); > + bool ill_altfmt =3D true; > int xlen =3D riscv_cpu_xlen(env); > bool vill =3D (s2 >> (xlen - 1)) & 0x1; > - target_ulong reserved =3D s2 & > - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, > - xlen - 1 - R_VTYPE_RESERVED_= SHIFT); > uint16_t vlen =3D cpu->cfg.vlenb << 3; > int8_t lmul; > > @@ -63,7 +77,22 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target= _ulong s1, > } > } > > - if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D= 0)) { > + switch (vsew) { > + case MO_8: > + ill_altfmt &=3D !(cpu->cfg.ext_zvfbfa); > + break; > + case MO_16: > + ill_altfmt &=3D !(cpu->cfg.ext_zvfbfa); > + break; > + default: > + break; > + } > + > + if (altfmt && ill_altfmt) { > + vill =3D true; > + } > + > + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) !=3D 0= )) { > /* only set vill bit. */ > env->vill =3D 1; > env->vtype =3D 0; > -- > 2.52.0 > >