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Sun, 16 Feb 2025 21:13:50 -0800 (PST) MIME-Version: 1.0 References: <20250212213249.45574-1-philmd@linaro.org> <20250212213249.45574-8-philmd@linaro.org> In-Reply-To: <20250212213249.45574-8-philmd@linaro.org> From: Alistair Francis Date: Mon, 17 Feb 2025 15:13:24 +1000 X-Gm-Features: AWEUYZmv67m3XmTIits4RJB-bziIKwvj9-Z5SoI2Gg3n5V1DOu6g7cZ4JnKw4-o Message-ID: Subject: Re: [PATCH v3 07/19] target/riscv: Convert misa_mxl_max using GLib macros To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Paolo Bonzini , Richard Henderson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::930; envelope-from=alistair23@gmail.com; helo=mail-ua1-x930.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Feb 13, 2025 at 7:34=E2=80=AFAM Philippe Mathieu-Daud=C3=A9 wrote: > > Use GLib conversion macros to pass misa_mxl_max as > riscv_cpu_class_init() class data. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f3ad7f88f0e..9fe1b23a297 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2955,7 +2955,7 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) > { > RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); > > - mcc->misa_mxl_max =3D (RISCVMXL)(uintptr_t)data; > + mcc->misa_mxl_max =3D (RISCVMXL)GPOINTER_TO_UINT(data); > riscv_cpu_validate_misa_mxl(mcc); > } > > @@ -3057,7 +3057,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) > .parent =3D TYPE_RISCV_CPU, \ > .instance_init =3D (initfn), \ > .class_init =3D riscv_cpu_class_init, \ > - .class_data =3D (void *)(misa_mxl_max) \ > + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ > } > > #define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ > @@ -3066,7 +3066,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) > .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ > .instance_init =3D (initfn), \ > .class_init =3D riscv_cpu_class_init, \ > - .class_data =3D (void *)(misa_mxl_max) \ > + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ > } > > #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ > @@ -3075,7 +3075,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) > .parent =3D TYPE_RISCV_VENDOR_CPU, \ > .instance_init =3D (initfn), \ > .class_init =3D riscv_cpu_class_init, \ > - .class_data =3D (void *)(misa_mxl_max) \ > + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ > } > > #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ > @@ -3084,7 +3084,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) > .parent =3D TYPE_RISCV_BARE_CPU, \ > .instance_init =3D (initfn), \ > .class_init =3D riscv_cpu_class_init, \ > - .class_data =3D (void *)(misa_mxl_max) \ > + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ > } > > #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ > @@ -3093,7 +3093,7 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, = char *nodename) > .parent =3D TYPE_RISCV_BARE_CPU, \ > .instance_init =3D (initfn), \ > .class_init =3D riscv_cpu_class_init, \ > - .class_data =3D (void *)(misa_mxl_max) \ > + .class_data =3D GUINT_TO_POINTER(misa_mxl_max) \ > } > > static const TypeInfo riscv_cpu_type_infos[] =3D { > -- > 2.47.1 > >