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From: Alistair Francis <alistair23@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Peter Crosthwaite" <crosthwaite.peter@gmail.com>,
	"Andrew Jeffery" <andrew@aj.id.au>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-arm <qemu-arm@nongnu.org>, "Joel Stanley" <joel@jms.id.au>
Subject: Re: [Qemu-devel] [PATCH 3/4] aspeed/smc: Add dummy data register
Date: Thu, 24 Jan 2019 13:29:31 -0800	[thread overview]
Message-ID: <CAKmqyKN3xpBkB5C52RcQOvs-Ra8hmcUETP3FgGRyCntgtp_0Pg@mail.gmail.com> (raw)
In-Reply-To: <20190124140519.13838-4-clg@kaod.org>

On Thu, Jan 24, 2019 at 6:06 AM Cédric Le Goater <clg@kaod.org> wrote:
>
> The SMC controllers have a register containing the byte that will be
> used as dummy output. It can be modified by software.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/ssi/aspeed_smc.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 6045ca11b969..9f3b6f4b4501 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -98,8 +98,8 @@
>  /* Misc Control Register #1 */
>  #define R_MISC_CTRL1      (0x50 / 4)
>
> -/* Misc Control Register #2 */
> -#define R_MISC_CTRL2      (0x54 / 4)
> +/* SPI dummy cycle data */
> +#define R_DUMMY_DATA      (0x54 / 4)
>
>  /* DMA Control/Status Register */
>  #define R_DMA_CTRL        (0x80 / 4)
> @@ -529,7 +529,7 @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
>       */
>      if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
>          for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
> -            ssi_transfer(fl->controller->spi, 0xFF);
> +            ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
>          }
>      }
>  }
> @@ -664,6 +664,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
>          addr == s->r_timings ||
>          addr == s->r_ce_ctrl ||
>          addr == R_INTR_CTRL ||
> +        addr == R_DUMMY_DATA ||
>          (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
>          (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
>          return s->regs[addr];
> @@ -697,6 +698,8 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
>          if (value != s->regs[R_SEG_ADDR0 + cs]) {
>              aspeed_smc_flash_set_segment(s, cs, value);
>          }
> +    } else if (addr == R_DUMMY_DATA) {
> +        s->regs[addr] = value & 0xff;
>      } else {
>          qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
>                        __func__, addr);
> --
> 2.20.1
>
>

  parent reply	other threads:[~2019-01-24 21:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-24 14:05 [Qemu-devel] [PATCH 0/4] aspeed/smc: add fast read support under User command mode Cédric Le Goater
2019-01-24 14:05 ` [Qemu-devel] [PATCH 1/4] aspeed/smc: fix default read value Cédric Le Goater
2019-01-24 20:05   ` Joel Stanley
2019-01-24 14:05 ` [Qemu-devel] [PATCH 2/4] aspeed/smc: define registers for all possible CS Cédric Le Goater
2019-01-24 20:08   ` Joel Stanley
2019-01-24 14:05 ` [Qemu-devel] [PATCH 3/4] aspeed/smc: Add dummy data register Cédric Le Goater
2019-01-24 20:11   ` Joel Stanley
2019-01-24 21:29   ` Alistair Francis [this message]
2019-01-24 14:05 ` [Qemu-devel] [PATCH 4/4] aspeed/smc: snoop SPI transfers to fake dummy cycles Cédric Le Goater
2019-01-28 12:32 ` [Qemu-devel] [PATCH 0/4] aspeed/smc: add fast read support under User command mode Peter Maydell

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