From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: guoren@linux.alibaba.com,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wxy194768@alibaba-inc.com,
Chih-Min Chao <chihmin.chao@sifive.com>,
wenmeng_zhang@c-sky.com, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v7 29/61] target/riscv: vector narrowing fixed-point clip instructions
Date: Fri, 17 Apr 2020 14:45:22 -0700 [thread overview]
Message-ID: <CAKmqyKN3yV5nC5punoLcY3+dA72se7OhxLACCgqE_ufnUBb50A@mail.gmail.com> (raw)
In-Reply-To: <20200330153633.15298-30-zhiwei_liu@c-sky.com>
On Mon, Mar 30, 2020 at 9:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 13 +++
> target/riscv/insn32.decode | 6 +
> target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
> target/riscv/vector_helper.c | 141 ++++++++++++++++++++++++
> 4 files changed, 168 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index f36f840714..7f7fdcb451 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -784,3 +784,16 @@ DEF_HELPER_6(vssra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +
> +DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 2ecac3d96d..8b898f9bad 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -437,6 +437,12 @@ vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
> vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
> vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
> vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
> +vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm
> +vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm
> +vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
> +vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
> +vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
> +vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
>
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index d5aaf18a07..d03ec2688f 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -1799,3 +1799,11 @@ GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
> GEN_OPIVX_TRANS(vssra_vx, opivx_check)
> GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
> GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
> +
> +/* Vector Narrowing Fixed-Point Clip Instructions */
> +GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
> +GEN_OPIVV_NARROW_TRANS(vnclip_vv)
> +GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
> +GEN_OPIVX_NARROW_TRANS(vnclip_vx)
> +GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
> +GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 00ee42ea83..502656d005 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -874,6 +874,12 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
> #define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
> #define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
> #define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
> +#define NOP_SSS_B int8_t, int8_t, int16_t, int8_t, int16_t
> +#define NOP_SSS_H int16_t, int16_t, int32_t, int16_t, int32_t
> +#define NOP_SSS_W int32_t, int32_t, int64_t, int32_t, int64_t
> +#define NOP_UUU_B uint8_t, uint8_t, uint16_t, uint8_t, uint16_t
> +#define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t
> +#define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t
>
> /* operation of two vector elements */
> typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
> @@ -3008,6 +3014,7 @@ vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b)
> res = (a >> shift) + round;
> return res;
> }
> +
> RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
> RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
> RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
> @@ -3025,3 +3032,137 @@ GEN_VEXT_VX_RM(vssra_vx_b, 1, 1, clearb)
> GEN_VEXT_VX_RM(vssra_vx_h, 2, 2, clearh)
> GEN_VEXT_VX_RM(vssra_vx_w, 4, 4, clearl)
> GEN_VEXT_VX_RM(vssra_vx_d, 8, 8, clearq)
> +
> +/* Vector Narrowing Fixed-Point Clip Instructions */
> +static inline int8_t
> +vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8_t b)
> +{
> + uint8_t round, shift = b & 0xf;
> + int16_t res;
> +
> + round = get_round(vxrm, a, shift);
> + res = (a >> shift) + round;
> + if (res > INT8_MAX) {
> + env->vxsat = 0x1;
> + return INT8_MAX;
> + } else if (res < INT8_MIN) {
> + env->vxsat = 0x1;
> + return INT8_MIN;
> + } else {
> + return res;
> + }
> +}
> +
> +static inline int16_t
> +vnclip16(CPURISCVState *env, int vxrm, int32_t a, int16_t b)
> +{
> + uint8_t round, shift = b & 0x1f;
> + int32_t res;
> +
> + round = get_round(vxrm, a, shift);
> + res = (a >> shift) + round;
> + if (res > INT16_MAX) {
> + env->vxsat = 0x1;
> + return INT16_MAX;
> + } else if (res < INT16_MIN) {
> + env->vxsat = 0x1;
> + return INT16_MIN;
> + } else {
> + return res;
> + }
> +}
> +
> +static inline int32_t
> +vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
> +{
> + uint8_t round, shift = b & 0x3f;
> + int64_t res;
> +
> + round = get_round(vxrm, a, shift);
> + res = (a >> shift) + round;
> + if (res > INT32_MAX) {
> + env->vxsat = 0x1;
> + return INT32_MAX;
> + } else if (res < INT32_MIN) {
> + env->vxsat = 0x1;
> + return INT32_MIN;
> + } else {
> + return res;
> + }
> +}
> +
> +RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
> +RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
> +RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
> +GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb)
> +GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl)
> +
> +RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8)
> +RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16)
> +RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32)
> +GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb)
> +GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh)
> +GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl)
> +
> +static inline uint8_t
> +vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
> +{
> + uint8_t round, shift = b & 0xf;
> + uint16_t res;
> +
> + round = get_round(vxrm, a, shift);
> + res = (a >> shift) + round;
> + if (res > UINT8_MAX) {
> + env->vxsat = 0x1;
> + return UINT8_MAX;
> + } else {
> + return res;
> + }
> +}
> +
> +static inline uint16_t
> +vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b)
> +{
> + uint8_t round, shift = b & 0x1f;
> + uint32_t res;
> +
> + round = get_round(vxrm, a, shift);
> + res = (a >> shift) + round;
> + if (res > UINT16_MAX) {
> + env->vxsat = 0x1;
> + return UINT16_MAX;
> + } else {
> + return res;
> + }
> +}
> +
> +static inline uint32_t
> +vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
> +{
> + uint8_t round, shift = b & 0x3f;
> + int64_t res;
> +
> + round = get_round(vxrm, a, shift);
> + res = (a >> shift) + round;
> + if (res > UINT32_MAX) {
> + env->vxsat = 0x1;
> + return UINT32_MAX;
> + } else {
> + return res;
> + }
> +}
> +
> +RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
> +RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
> +RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
> +GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb)
> +GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl)
> +
> +RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8)
> +RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16)
> +RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
> +GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb)
> +GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh)
> +GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
> --
> 2.23.0
>
next prev parent reply other threads:[~2020-04-17 21:54 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 15:35 [PATCH v7 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 07/61] target/riscv: add vector index " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 11/61] target/riscv: vector widening " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 22/61] target/riscv: vector widening " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-03-30 16:46 ` Alistair Francis
2020-03-30 15:35 ` [PATCH v7 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-04-02 17:23 ` Alistair Francis
2020-03-30 15:35 ` [PATCH v7 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-04-02 17:25 ` Alistair Francis
2020-03-30 15:35 ` [PATCH v7 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-04-02 22:53 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-04-17 21:55 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-04-17 21:45 ` Alistair Francis [this message]
2020-03-30 15:36 ` [PATCH v7 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-04-17 22:07 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 31/61] target/riscv: vector widening " LIU Zhiwei
2020-04-17 22:01 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-04-17 21:46 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-04-17 22:02 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 35/61] target/riscv: vector widening " LIU Zhiwei
2020-04-17 22:11 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-04-17 22:13 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-04-17 22:14 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-04-17 22:32 ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 43/61] target/riscv: widening " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 44/61] target/riscv: narrowing " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 48/61] target/riscv: vector widening " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-03-30 23:37 ` [PATCH v7 00/61] target/riscv: support vector extension v0.7.1 no-reply
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