From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Igor Mitsyanko" <i.mitsyanko@gmail.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
qemu-arm <qemu-arm@nongnu.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>
Subject: Re: [PATCH v2 2/4] hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
Date: Mon, 18 May 2020 09:43:02 -0700 [thread overview]
Message-ID: <CAKmqyKN4bSSdvAyoPjAYZoiMLuPT=SDrVkq5OSb3Pk4Q0Jhp4w@mail.gmail.com> (raw)
In-Reply-To: <20200518140309.5220-3-f4bug@amsat.org>
On Mon, May 18, 2020 at 7:03 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> hw_error() calls exit(). This a bit overkill when we can log
> the accesses as unimplemented or guest error.
>
> When fuzzing the devices, we don't want the whole process to
> exit. Replace some hw_error() calls by qemu_log_mask().
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/pxa2xx_gpio.c | 7 ++++---
> hw/display/pxa2xx_lcd.c | 8 +++++---
> hw/dma/pxa2xx_dma.c | 14 +++++++++-----
> 3 files changed, 18 insertions(+), 11 deletions(-)
>
> diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
> index f8df3cc227..a01db54a51 100644
> --- a/hw/arm/pxa2xx_gpio.c
> +++ b/hw/arm/pxa2xx_gpio.c
> @@ -9,7 +9,6 @@
>
> #include "qemu/osdep.h"
> #include "cpu.h"
> -#include "hw/hw.h"
> #include "hw/irq.h"
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> @@ -199,7 +198,8 @@ static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
> return s->status[bank];
>
> default:
> - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> + __func__, offset);
> }
>
> return 0;
> @@ -252,7 +252,8 @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
> break;
>
> default:
> - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> + __func__, offset);
> }
> }
>
> diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c
> index 464e93161a..d5f2e82a4e 100644
> --- a/hw/display/pxa2xx_lcd.c
> +++ b/hw/display/pxa2xx_lcd.c
> @@ -11,7 +11,7 @@
> */
>
> #include "qemu/osdep.h"
> -#include "hw/hw.h"
> +#include "qemu/log.h"
> #include "hw/irq.h"
> #include "migration/vmstate.h"
> #include "ui/console.h"
> @@ -407,7 +407,8 @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
>
> default:
> fail:
> - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> + __func__, offset);
> }
>
> return 0;
> @@ -562,7 +563,8 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
>
> default:
> fail:
> - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> + __func__, offset);
> }
> }
>
> diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c
> index 88ed4b6ff1..8a2eeb32bc 100644
> --- a/hw/dma/pxa2xx_dma.c
> +++ b/hw/dma/pxa2xx_dma.c
> @@ -9,6 +9,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/log.h"
> #include "hw/hw.h"
> #include "hw/irq.h"
> #include "hw/qdev-properties.h"
> @@ -268,7 +269,8 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
> unsigned int channel;
>
> if (size != 4) {
> - hw_error("%s: Bad access width\n", __func__);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
> + __func__, size);
> return 5;
> }
>
> @@ -315,8 +317,8 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset,
> return s->chan[channel].cmd;
> }
> }
> -
> - hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> + __func__, offset);
> return 7;
> }
>
> @@ -327,7 +329,8 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
> unsigned int channel;
>
> if (size != 4) {
> - hw_error("%s: Bad access width\n", __func__);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad access width %u\n",
> + __func__, size);
> return;
> }
>
> @@ -420,7 +423,8 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset,
> break;
> }
> fail:
> - hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset);
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> + __func__, offset);
> }
> }
>
> --
> 2.21.3
>
>
next prev parent reply other threads:[~2020-05-18 16:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-18 14:03 [PATCH v2 0/4] hw/arm: Replace hw_error() by qemu_log_mask() Philippe Mathieu-Daudé
2020-05-18 14:03 ` [PATCH v2 1/4] hw/arm/integratorcp: " Philippe Mathieu-Daudé
2020-05-18 16:41 ` Alistair Francis
2020-05-18 14:03 ` [PATCH v2 2/4] hw/arm/pxa2xx: " Philippe Mathieu-Daudé
2020-05-18 16:43 ` Alistair Francis [this message]
2020-05-18 14:03 ` [PATCH v2 3/4] hw/char/xilinx_uartlite: " Philippe Mathieu-Daudé
2020-05-18 16:43 ` Alistair Francis
2020-05-18 14:03 ` [PATCH v2 4/4] hw/timer/exynos4210_mct: " Philippe Mathieu-Daudé
2020-05-18 16:44 ` Alistair Francis
2020-05-21 16:05 ` [PATCH v2 0/4] hw/arm: " Peter Maydell
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