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That's all we know. X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Aug 14, 2020 at 9:43 AM Bin Meng wrote: > > From: Bin Meng > > Currently the reset vector address is hard-coded in a RISC-V CPU's > instance_init() routine. In a real world we can have 2 exact same > CPUs except for the reset vector address, which is pretty common in > the RISC-V core IP licensing business. > > Normally reset vector address is a configurable parameter. Let's > create a 64-bit property to store the reset vector address which > covers both 32-bit and 64-bit CPUs. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 228b9bd..8067a26 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -518,6 +518,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index a804a5d..d34bcfa 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -291,6 +291,7 @@ typedef struct RISCVCPU { > uint16_t elen; > bool mmu; > bool pmp; > + uint64_t resetvec; > } cfg; > } RISCVCPU; > > -- > 2.7.4 > >