From: Alistair Francis <alistair23@gmail.com>
To: Weiwei Li <liweiwei@iscas.ac.cn>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
richard.henderson@linaro.org, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com
Subject: Re: [PATCH v5 03/13] target/riscv: Make the short cut really work in pmp_hart_has_privs
Date: Wed, 17 May 2023 12:07:29 +1000 [thread overview]
Message-ID: <CAKmqyKN6bYv8pN7adiq=B6oiFLkCj4s3=aWjwt-49Et1w2wnhg@mail.gmail.com> (raw)
In-Reply-To: <20230428143621.142390-4-liweiwei@iscas.ac.cn>
On Sat, Apr 29, 2023 at 12:38 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Return the result directly for short cut, since We needn't do the
> following check on the PMP entries if there is no PMP rules.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/pmp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index ad20a319c1..86abe1e7cd 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -316,6 +316,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
> allowed_privs, mode)) {
> ret = MAX_RISCV_PMPS;
> }
> + return ret;
> }
>
> if (size == 0) {
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2023-05-17 2:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 14:36 [PATCH v5 00/13] target/riscv: Fix PMP related problem Weiwei Li
2023-04-28 14:36 ` [PATCH v5 01/13] target/riscv: Update pmp_get_tlb_size() Weiwei Li
2023-05-17 2:00 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 02/13] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Weiwei Li
2023-05-17 2:05 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 03/13] target/riscv: Make the short cut really work in pmp_hart_has_privs Weiwei Li
2023-05-17 2:07 ` Alistair Francis [this message]
2023-04-28 14:36 ` [PATCH v5 04/13] target/riscv: Change the return type of pmp_hart_has_privs() to bool Weiwei Li
2023-05-17 2:08 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 05/13] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Weiwei Li
2023-05-17 2:14 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 06/13] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Weiwei Li
2023-05-17 2:09 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 07/13] target/riscv: Flush TLB when MMWP or MML bits are changed Weiwei Li
2023-05-17 2:12 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 08/13] target/riscv: Update the next rule addr in pmpaddr_csr_write() Weiwei Li
2023-05-17 2:21 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 09/13] target/riscv: Flush TLB when pmpaddr is updated Weiwei Li
2023-04-28 14:36 ` [PATCH v5 10/13] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Weiwei Li
2023-04-28 14:36 ` [PATCH v5 11/13] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 Weiwei Li
2023-04-28 14:36 ` [PATCH v5 12/13] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Weiwei Li
2023-05-17 2:23 ` Alistair Francis
2023-04-28 14:36 ` [PATCH v5 13/13] target/riscv: Deny access if access is partially inside the PMP entry Weiwei Li
2023-05-17 2:23 ` Alistair Francis
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