From: Alistair Francis <alistair23@gmail.com>
To: Ajeet Singh <itachis6234@gmail.com>
Cc: qemu-devel@nongnu.org, Warner Losh <imp@bsdimp.com>,
Mark Corbin <mark@dibsco.co.uk>,
Ajeet Singh <itachis@freebsd.org>
Subject: Re: [PATCH v5 00/17] bsd-user: Comprehensive RISCV Support
Date: Mon, 9 Sep 2024 09:55:05 +1000 [thread overview]
Message-ID: <CAKmqyKN7E8jfAdJ9ym2cOTRuUEiNsCVqR+fKEhTB9rPSQP1Yjg@mail.gmail.com> (raw)
In-Reply-To: <20240907031927.1908-1-itachis@FreeBSD.org>
On Sat, Sep 7, 2024 at 1:25 PM Ajeet Singh <itachis6234@gmail.com> wrote:
>
> Key Changes Compared to Version 4:
> Minor formatting changes
>
> Mark Corbin (15):
> bsd-user: Implement RISC-V CPU initialization and main loop
> bsd-user: Add RISC-V CPU execution loop and syscall handling
> bsd-user: Implement RISC-V CPU register cloning and reset functions
> bsd-user: Implement RISC-V TLS register setup
> bsd-user: Add RISC-V ELF definitions and hardware capability detection
> bsd-user: Define RISC-V register structures and register copying
> bsd-user: Add RISC-V signal trampoline setup function
> bsd-user: Implement RISC-V sysarch system call emulation
> bsd-user: Add RISC-V thread setup and initialization support
> bsd-user: Define RISC-V VM parameters and helper functions
> bsd-user: Define RISC-V system call structures and constants
> bsd-user: Define RISC-V signal handling structures and constants
> bsd-user: Implement RISC-V signal trampoline setup functions
> bsd-user: Implement 'get_mcontext' for RISC-V
> bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
>
> Warner Losh (2):
> bsd-user: Add generic RISC-V64 target definitions
> bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
>
> bsd-user/riscv/signal.c | 170 ++++++++++++++++++++++++++
> bsd-user/riscv/target.h | 20 +++
> bsd-user/riscv/target_arch.h | 27 ++++
> bsd-user/riscv/target_arch_cpu.c | 29 +++++
> bsd-user/riscv/target_arch_cpu.h | 147 ++++++++++++++++++++++
> bsd-user/riscv/target_arch_elf.h | 42 +++++++
> bsd-user/riscv/target_arch_reg.h | 88 +++++++++++++
> bsd-user/riscv/target_arch_signal.h | 75 ++++++++++++
> bsd-user/riscv/target_arch_sigtramp.h | 42 +++++++
> bsd-user/riscv/target_arch_sysarch.h | 41 +++++++
> bsd-user/riscv/target_arch_thread.h | 47 +++++++
> bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++
> bsd-user/riscv/target_syscall.h | 38 ++++++
> configs/targets/riscv64-bsd-user.mak | 4 +
> 14 files changed, 823 insertions(+)
> create mode 100644 bsd-user/riscv/signal.c
> create mode 100644 bsd-user/riscv/target.h
> create mode 100644 bsd-user/riscv/target_arch.h
> create mode 100644 bsd-user/riscv/target_arch_cpu.c
> create mode 100644 bsd-user/riscv/target_arch_cpu.h
> create mode 100644 bsd-user/riscv/target_arch_elf.h
> create mode 100644 bsd-user/riscv/target_arch_reg.h
> create mode 100644 bsd-user/riscv/target_arch_signal.h
> create mode 100644 bsd-user/riscv/target_arch_sigtramp.h
> create mode 100644 bsd-user/riscv/target_arch_sysarch.h
> create mode 100644 bsd-user/riscv/target_arch_thread.h
> create mode 100644 bsd-user/riscv/target_arch_vmparam.h
> create mode 100644 bsd-user/riscv/target_syscall.h
> create mode 100644 configs/targets/riscv64-bsd-user.mak
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> --
> 2.34.1
>
>
prev parent reply other threads:[~2024-09-08 23:56 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-07 3:19 [PATCH v5 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-09-07 3:19 ` [PATCH v5 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
2024-09-08 23:55 ` Alistair Francis [this message]
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