From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
Date: Fri, 19 Mar 2021 09:19:11 -0400 [thread overview]
Message-ID: <CAKmqyKN7TeyLUYZ2kdLb1iOBLeVGuvpx55NmSXeDM7MdxxVG1w@mail.gmail.com> (raw)
In-Reply-To: <20c52b91-3ddb-f384-3094-7efb344ca5ef@linaro.org>
On Thu, Mar 18, 2021 at 9:25 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 3/17/21 11:40 AM, Alistair Francis wrote:
> > result = riscv_csrrw_debug(env, n - 32, &val,
> > 0, 0);
> > - if (result == 0) {
> > + if (result != RISCV_EXCP_NONE) {
>
> This was intending == NONE. I.e. no exception raised, let gdb proceed.
Good catch! Fixed.
Alistair
>
>
> r~
prev parent reply other threads:[~2021-03-19 13:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 17:39 [PATCH v1 0/5] RISC-V: Convert the CSR access functions to use Alistair Francis
2021-03-17 17:39 ` [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-03-18 1:58 ` Bin Meng
2021-03-19 13:19 ` Alistair Francis
2021-03-17 17:39 ` [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates Alistair Francis
2021-03-17 19:44 ` Richard Henderson
2021-03-19 13:17 ` Alistair Francis
2021-03-17 17:39 ` [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-03-17 17:39 ` [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations Alistair Francis
2021-03-17 17:40 ` [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access Alistair Francis
2021-03-18 13:25 ` Richard Henderson
2021-03-19 13:19 ` Alistair Francis [this message]
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