* [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
2024-06-05 6:31 [PATCH RESEND 0/6] Introduce extension implied rules frank.chang
@ 2024-06-05 6:31 ` frank.chang
2024-06-11 1:35 ` Alistair Francis
2024-06-05 6:31 ` [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: frank.chang @ 2024-06-05 6:31 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offset of the extension defined in RISCVCPUConfig. 'ext' will also
serve as the key of the hash tables to look up the rule in the following
commit.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 8 ++++++++
target/riscv/cpu.h | 18 ++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cee6fc4a9a..c7e5cec7ef 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2242,6 +2242,14 @@ RISCVCPUProfile *riscv_profiles[] = {
NULL,
};
+RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
+ NULL
+};
+
+RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
+ NULL
+};
+
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1501868008..b5a036cf27 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -122,6 +122,24 @@ typedef enum {
EXT_STATUS_DIRTY,
} RISCVExtStatus;
+typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule;
+
+struct riscv_cpu_implied_exts_rule {
+ /* Bitmask indicates the rule enabled status for the harts. */
+ uint64_t enabled;
+ /* True if this is a MISA implied rule. */
+ bool is_misa;
+ /* ext is MISA bit if is_misa flag is true, else extension offset. */
+ const uint32_t ext;
+ const uint32_t implied_misas;
+ const uint32_t implied_exts[];
+};
+
+extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[];
+extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[];
+
+#define RISCV_IMPLIED_EXTS_RULE_END -1
+
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
2024-06-05 6:31 ` [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition frank.chang
@ 2024-06-11 1:35 ` Alistair Francis
2024-06-11 1:56 ` Frank Chang
0 siblings, 1 reply; 13+ messages in thread
From: Alistair Francis @ 2024-06-11 1:35 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
On Wed, Jun 5, 2024 at 4:35 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> RISCVCPUImpliedExtsRule is created to store the implied rules.
> 'is_misa' flag is used to distinguish whether the rule is derived
> from the MISA or other extensions.
> 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
> the offset of the extension defined in RISCVCPUConfig. 'ext' will also
> serve as the key of the hash tables to look up the rule in the following
> commit.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu.h | 18 ++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cee6fc4a9a..c7e5cec7ef 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2242,6 +2242,14 @@ RISCVCPUProfile *riscv_profiles[] = {
> NULL,
> };
>
> +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> + NULL
> +};
> +
> +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
> + NULL
> +};
> +
> static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1501868008..b5a036cf27 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -122,6 +122,24 @@ typedef enum {
> EXT_STATUS_DIRTY,
> } RISCVExtStatus;
>
> +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule;
> +
> +struct riscv_cpu_implied_exts_rule {
> + /* Bitmask indicates the rule enabled status for the harts. */
> + uint64_t enabled;
I'm not clear why we need this
Alistair
> + /* True if this is a MISA implied rule. */
> + bool is_misa;
> + /* ext is MISA bit if is_misa flag is true, else extension offset. */
> + const uint32_t ext;
> + const uint32_t implied_misas;
> + const uint32_t implied_exts[];
> +};
> +
> +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[];
> +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[];
> +
> +#define RISCV_IMPLIED_EXTS_RULE_END -1
> +
> #define MMU_USER_IDX 3
>
> #define MAX_RISCV_PMPS (16)
> --
> 2.43.2
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition
2024-06-11 1:35 ` Alistair Francis
@ 2024-06-11 1:56 ` Frank Chang
0 siblings, 0 replies; 13+ messages in thread
From: Frank Chang @ 2024-06-11 1:56 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
[-- Attachment #1: Type: text/plain, Size: 2913 bytes --]
Hi Alistair,
On Tue, Jun 11, 2024 at 9:35 AM Alistair Francis <alistair23@gmail.com>
wrote:
> On Wed, Jun 5, 2024 at 4:35 PM <frank.chang@sifive.com> wrote:
> >
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > RISCVCPUImpliedExtsRule is created to store the implied rules.
> > 'is_misa' flag is used to distinguish whether the rule is derived
> > from the MISA or other extensions.
> > 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
> > the offset of the extension defined in RISCVCPUConfig. 'ext' will also
> > serve as the key of the hash tables to look up the rule in the following
> > commit.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > target/riscv/cpu.c | 8 ++++++++
> > target/riscv/cpu.h | 18 ++++++++++++++++++
> > 2 files changed, 26 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index cee6fc4a9a..c7e5cec7ef 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -2242,6 +2242,14 @@ RISCVCPUProfile *riscv_profiles[] = {
> > NULL,
> > };
> >
> > +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> > + NULL
> > +};
> > +
> > +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
> > + NULL
> > +};
> > +
> > static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 1501868008..b5a036cf27 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -122,6 +122,24 @@ typedef enum {
> > EXT_STATUS_DIRTY,
> > } RISCVExtStatus;
> >
> > +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule;
> > +
> > +struct riscv_cpu_implied_exts_rule {
> > + /* Bitmask indicates the rule enabled status for the harts. */
> > + uint64_t enabled;
>
> I'm not clear why we need this
>
This is because a rule may be implied more than once.
e.g. Zcf implies RVF, Zfa also implies RVF.
There's no need to check RVF's implied rule again for Zfa after Zcf's
implied rules are enabled.
The implied rules are checked recursively, so once the rule has been
enabled (per-CPU basis),
the rule (and all its implied rules) will not be rechecked.
Regards,
Frank Chang
> Alistair
>
> > + /* True if this is a MISA implied rule. */
> > + bool is_misa;
> > + /* ext is MISA bit if is_misa flag is true, else extension offset.
> */
> > + const uint32_t ext;
> > + const uint32_t implied_misas;
> > + const uint32_t implied_exts[];
> > +};
> > +
> > +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[];
> > +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[];
> > +
> > +#define RISCV_IMPLIED_EXTS_RULE_END -1
> > +
> > #define MMU_USER_IDX 3
> >
> > #define MAX_RISCV_PMPS (16)
> > --
> > 2.43.2
> >
> >
>
[-- Attachment #2: Type: text/html, Size: 4093 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers
2024-06-05 6:31 [PATCH RESEND 0/6] Introduce extension implied rules frank.chang
2024-06-05 6:31 ` [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition frank.chang
@ 2024-06-05 6:31 ` frank.chang
2024-06-12 1:21 ` Frank Chang
2024-06-05 6:31 ` [PATCH RESEND 3/6] target/riscv: Add MISA implied rules frank.chang
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: frank.chang @ 2024-06-05 6:31 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks implies
Zvksed, etc., removing the need to check the implied rules of Zvksg
before Zvks.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/tcg/tcg-cpu.c | 89 ++++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 683f604d9f..899d605d36 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -36,6 +36,9 @@
static GHashTable *multi_ext_user_opts;
static GHashTable *misa_ext_user_opts;
+static GHashTable *misa_implied_rules;
+static GHashTable *ext_implied_rules;
+
static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
{
return g_hash_table_contains(multi_ext_user_opts,
@@ -833,11 +836,95 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
}
}
+static void riscv_cpu_init_implied_exts_rules(void)
+{
+ RISCVCPUImpliedExtsRule *rule;
+ int i;
+
+ for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
+ g_hash_table_insert(misa_implied_rules, GUINT_TO_POINTER(rule->ext),
+ (gpointer)rule);
+ }
+
+ for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
+ g_hash_table_insert(ext_implied_rules, GUINT_TO_POINTER(rule->ext),
+ (gpointer)rule);
+ }
+}
+
+static void cpu_enable_implied_rule(RISCVCPU *cpu,
+ RISCVCPUImpliedExtsRule *rule)
+{
+ CPURISCVState *env = &cpu->env;
+ RISCVCPUImpliedExtsRule *ir;
+ target_ulong hartid = 0;
+ int i;
+
+#if !defined(CONFIG_USER_ONLY)
+ hartid = env->mhartid;
+#endif
+
+ if (!(rule->enabled & BIT_ULL(hartid))) {
+ /* Enable the implied MISAs. */
+ if (rule->implied_misas) {
+ riscv_cpu_set_misa_ext(env, env->misa_ext | rule->implied_misas);
+
+ for (i = 0; misa_bits[i] != 0; i++) {
+ if (rule->implied_misas & misa_bits[i]) {
+ ir = g_hash_table_lookup(misa_implied_rules,
+ GUINT_TO_POINTER(misa_bits[i]));
+
+ if (ir) {
+ cpu_enable_implied_rule(cpu, ir);
+ }
+ }
+ }
+ }
+
+ /* Enable the implied extensions. */
+ for (i = 0; rule->implied_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) {
+ cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true);
+
+ ir = g_hash_table_lookup(ext_implied_rules,
+ GUINT_TO_POINTER(rule->implied_exts[i]));
+
+ if (ir) {
+ cpu_enable_implied_rule(cpu, ir);
+ }
+ }
+
+ rule->enabled |= BIT_ULL(hartid);
+ }
+}
+
+static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
+{
+ RISCVCPUImpliedExtsRule *rule;
+ int i;
+
+ /* Enable the implied MISAs. */
+ for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
+ if (riscv_has_ext(&cpu->env, rule->ext)) {
+ cpu_enable_implied_rule(cpu, rule);
+ }
+ }
+
+ /* Enable the implied extensions. */
+ for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
+ if (isa_ext_is_enabled(cpu, rule->ext)) {
+ cpu_enable_implied_rule(cpu, rule);
+ }
+ }
+}
+
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
+ riscv_cpu_init_implied_exts_rules();
+ riscv_cpu_enable_implied_rules(cpu);
+
riscv_cpu_validate_misa_priv(env, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -1343,6 +1430,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+ misa_implied_rules = g_hash_table_new(NULL, g_direct_equal);
+ ext_implied_rules = g_hash_table_new(NULL, g_direct_equal);
riscv_cpu_add_user_properties(obj);
if (riscv_cpu_has_max_extensions(obj)) {
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers
2024-06-05 6:31 ` [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
@ 2024-06-12 1:21 ` Frank Chang
0 siblings, 0 replies; 13+ messages in thread
From: Frank Chang @ 2024-06-12 1:21 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
[-- Attachment #1: Type: text/plain, Size: 5072 bytes --]
On Wed, Jun 5, 2024 at 2:32 PM <frank.chang@sifive.com> wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
> ordering requirement. For example, Zvksg implies Zvks, Zvks implies
> Zvksed, etc., removing the need to check the implied rules of Zvksg
> before Zvks.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/tcg/tcg-cpu.c | 89 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 683f604d9f..899d605d36 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -36,6 +36,9 @@
> static GHashTable *multi_ext_user_opts;
> static GHashTable *misa_ext_user_opts;
>
> +static GHashTable *misa_implied_rules;
> +static GHashTable *ext_implied_rules;
> +
> static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> {
> return g_hash_table_contains(multi_ext_user_opts,
> @@ -833,11 +836,95 @@ static void riscv_cpu_validate_profiles(RISCVCPU
> *cpu)
> }
> }
>
> +static void riscv_cpu_init_implied_exts_rules(void)
> +{
> + RISCVCPUImpliedExtsRule *rule;
> + int i;
> +
> + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> + g_hash_table_insert(misa_implied_rules,
> GUINT_TO_POINTER(rule->ext),
> + (gpointer)rule);
> + }
> +
> + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> + g_hash_table_insert(ext_implied_rules,
> GUINT_TO_POINTER(rule->ext),
> + (gpointer)rule);
> + }
> +}
> +
> +static void cpu_enable_implied_rule(RISCVCPU *cpu,
> + RISCVCPUImpliedExtsRule *rule)
> +{
> + CPURISCVState *env = &cpu->env;
> + RISCVCPUImpliedExtsRule *ir;
> + target_ulong hartid = 0;
> + int i;
> +
> +#if !defined(CONFIG_USER_ONLY)
> + hartid = env->mhartid;
> +#endif
> +
> + if (!(rule->enabled & BIT_ULL(hartid))) {
> + /* Enable the implied MISAs. */
> + if (rule->implied_misas) {
> + riscv_cpu_set_misa_ext(env, env->misa_ext |
> rule->implied_misas);
> +
> + for (i = 0; misa_bits[i] != 0; i++) {
> + if (rule->implied_misas & misa_bits[i]) {
> + ir = g_hash_table_lookup(misa_implied_rules,
> +
> GUINT_TO_POINTER(misa_bits[i]));
> +
> + if (ir) {
> + cpu_enable_implied_rule(cpu, ir);
> + }
> + }
> + }
> + }
> +
> + /* Enable the implied extensions. */
> + for (i = 0; rule->implied_exts[i] != RISCV_IMPLIED_EXTS_RULE_END;
> i++) {
> + cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true);
> +
> + ir = g_hash_table_lookup(ext_implied_rules,
> +
> GUINT_TO_POINTER(rule->implied_exts[i]));
> +
> + if (ir) {
> + cpu_enable_implied_rule(cpu, ir);
> + }
> + }
> +
> + rule->enabled |= BIT_ULL(hartid);
>
Should I use the qatomic API here to set the enabled bitmask?
This wouldn't impact the results but it may cause the implied rules
to be traversed and re-enabled (which has no harm) if the enabled bit
of a hart is accidentally cleared by another harts.
> + }
> +}
> +
> +static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
> +{
> + RISCVCPUImpliedExtsRule *rule;
> + int i;
> +
> + /* Enable the implied MISAs. */
> + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> + if (riscv_has_ext(&cpu->env, rule->ext)) {
> + cpu_enable_implied_rule(cpu, rule);
> + }
> + }
> +
> + /* Enable the implied extensions. */
> + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> + if (isa_ext_is_enabled(cpu, rule->ext)) {
> + cpu_enable_implied_rule(cpu, rule);
> + }
> + }
> +}
> +
> void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> {
> CPURISCVState *env = &cpu->env;
> Error *local_err = NULL;
>
> + riscv_cpu_init_implied_exts_rules();
> + riscv_cpu_enable_implied_rules(cpu);
> +
> riscv_cpu_validate_misa_priv(env, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> @@ -1343,6 +1430,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
>
> misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> + misa_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> + ext_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> riscv_cpu_add_user_properties(obj);
>
> if (riscv_cpu_has_max_extensions(obj)) {
> --
> 2.43.2
>
>
[-- Attachment #2: Type: text/html, Size: 6439 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH RESEND 3/6] target/riscv: Add MISA implied rules
2024-06-05 6:31 [PATCH RESEND 0/6] Introduce extension implied rules frank.chang
2024-06-05 6:31 ` [PATCH RESEND 1/6] target/riscv: Introduce extension implied rules definition frank.chang
2024-06-05 6:31 ` [PATCH RESEND 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
@ 2024-06-05 6:31 ` frank.chang
2024-06-11 1:41 ` Alistair Francis
2024-06-05 6:31 ` [PATCH RESEND 4/6] target/riscv: Add standard extension " frank.chang
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: frank.chang @ 2024-06-05 6:31 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c7e5cec7ef..a6e9055c5f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2242,8 +2242,56 @@ RISCVCPUProfile *riscv_profiles[] = {
NULL,
};
+static RISCVCPUImpliedExtsRule RVA_IMPLIED = {
+ .is_misa = true,
+ .ext = RVA,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule RVD_IMPLIED = {
+ .is_misa = true,
+ .ext = RVD,
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule RVF_IMPLIED = {
+ .is_misa = true,
+ .ext = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule RVM_IMPLIED = {
+ .is_misa = true,
+ .ext = RVM,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zmmul),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
+ .is_misa = true,
+ .ext = RVV,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve64d),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
- NULL
+ &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
+ &RVM_IMPLIED, &RVV_IMPLIED, NULL
};
RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH RESEND 3/6] target/riscv: Add MISA implied rules
2024-06-05 6:31 ` [PATCH RESEND 3/6] target/riscv: Add MISA implied rules frank.chang
@ 2024-06-11 1:41 ` Alistair Francis
0 siblings, 0 replies; 13+ messages in thread
From: Alistair Francis @ 2024-06-11 1:41 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
On Wed, Jun 5, 2024 at 4:34 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add MISA extension implied rules to enable the implied extensions
> of MISA recursively.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c7e5cec7ef..a6e9055c5f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2242,8 +2242,56 @@ RISCVCPUProfile *riscv_profiles[] = {
> NULL,
> };
>
> +static RISCVCPUImpliedExtsRule RVA_IMPLIED = {
> + .is_misa = true,
> + .ext = RVA,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVD_IMPLIED = {
> + .is_misa = true,
> + .ext = RVD,
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVF_IMPLIED = {
> + .is_misa = true,
> + .ext = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVM_IMPLIED = {
> + .is_misa = true,
> + .ext = RVM,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zmmul),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
> + .is_misa = true,
> + .ext = RVV,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve64d),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> - NULL
> + &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> + &RVM_IMPLIED, &RVV_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
> --
> 2.43.2
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH RESEND 4/6] target/riscv: Add standard extension implied rules
2024-06-05 6:31 [PATCH RESEND 0/6] Introduce extension implied rules frank.chang
` (2 preceding siblings ...)
2024-06-05 6:31 ` [PATCH RESEND 3/6] target/riscv: Add MISA implied rules frank.chang
@ 2024-06-05 6:31 ` frank.chang
2024-06-11 1:45 ` Alistair Francis
2024-06-05 6:31 ` [PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule frank.chang
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: frank.chang @ 2024-06-05 6:31 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 340 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 340 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a6e9055c5f..80b238060a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2289,12 +2289,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
},
};
+static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcb),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCD_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcd),
+ .implied_misas = RVD,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCE_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zce),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp),
+ CPU_CFG_OFFSET(ext_zcmt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCF_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcf),
+ .implied_misas = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCMP_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcmp),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCMT_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcmt),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZDINX_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zdinx),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zfinx),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZFA_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfa),
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfbfmin),
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule ZFH_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfh),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zfhmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfhmin),
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule ZFINX_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfinx),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZHINX_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zhinx),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zhinxmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zhinxmin),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zfinx),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zicntr),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zihpm),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZK_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zk),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr),
+ CPU_CFG_OFFSET(ext_zkt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZKN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zkn),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
+ CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne),
+ CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZKS_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zks),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
+ CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed),
+ CPU_CFG_OFFSET(ext_zksh),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVBB_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvbb),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkb),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve32f),
+ .implied_misas = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve32x),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve64d),
+ .implied_misas = RVD,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve64f),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve64f),
+ .implied_misas = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve64x),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfbfmin),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32f),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfbfwma),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFH_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfh),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfhmin),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32f),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvkn),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb),
+ CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvknc),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvkng),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvknhb),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve64x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKS_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvks),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh),
+ CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvksc),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvksg),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
&RVM_IMPLIED, &RVV_IMPLIED, NULL
};
RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
+ &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED,
+ &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED,
+ &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED,
+ &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED,
+ &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
+ &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
+ &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
+ &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED,
+ &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
+ &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
+ &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
+ &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
NULL
};
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH RESEND 4/6] target/riscv: Add standard extension implied rules
2024-06-05 6:31 ` [PATCH RESEND 4/6] target/riscv: Add standard extension " frank.chang
@ 2024-06-11 1:45 ` Alistair Francis
0 siblings, 0 replies; 13+ messages in thread
From: Alistair Francis @ 2024-06-11 1:45 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
On Wed, Jun 5, 2024 at 4:35 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add standard extension implied rules to enable the implied extensions of
> the standard extension recursively.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 340 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 340 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a6e9055c5f..80b238060a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2289,12 +2289,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcb),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCD_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcd),
> + .implied_misas = RVD,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCE_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zce),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp),
> + CPU_CFG_OFFSET(ext_zcmt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCF_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcf),
> + .implied_misas = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCMP_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcmp),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCMT_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcmt),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZDINX_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zdinx),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zfinx),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFA_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfa),
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfbfmin),
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFH_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfh),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zfhmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfhmin),
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFINX_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfinx),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZHINX_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zhinx),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zhinxmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zhinxmin),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zfinx),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zicntr),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zihpm),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZK_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zk),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr),
> + CPU_CFG_OFFSET(ext_zkt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZKN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zkn),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
> + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne),
> + CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZKS_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zks),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
> + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed),
> + CPU_CFG_OFFSET(ext_zksh),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVBB_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvbb),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkb),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve32f),
> + .implied_misas = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve32x),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve64d),
> + .implied_misas = RVD,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve64f),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve64f),
> + .implied_misas = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve64x),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfbfmin),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32f),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfbfwma),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFH_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfh),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfhmin),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32f),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvkn),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb),
> + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvknc),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvkng),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvknhb),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve64x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKS_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvks),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh),
> + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvksc),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvksg),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> &RVM_IMPLIED, &RVV_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
> + &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED,
> + &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED,
> + &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED,
> + &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED,
> + &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
> + &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
> + &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
> + &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED,
> + &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
> + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
> + &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
> + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
> NULL
> };
>
> --
> 2.43.2
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule
2024-06-05 6:31 [PATCH RESEND 0/6] Introduce extension implied rules frank.chang
` (3 preceding siblings ...)
2024-06-05 6:31 ` [PATCH RESEND 4/6] target/riscv: Add standard extension " frank.chang
@ 2024-06-05 6:31 ` frank.chang
2024-06-05 6:31 ` [PATCH RESEND 6/6] target/riscv: Remove extension auto-update check statements frank.chang
2024-06-05 7:48 ` [PATCH RESEND 0/6] Introduce extension implied rules Jerry Zhang Jian
6 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2024-06-05 6:31 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/tcg/tcg-cpu.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 899d605d36..ed10ac799a 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -897,11 +897,45 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu,
}
}
+/* Zc extension has special implied rules that need to be handled separately. */
+static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ CPURISCVState *env = &cpu->env;
+
+ if (cpu->cfg.ext_zce) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
+
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+ }
+
+ /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */
+ if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+
+ if (riscv_has_ext(env, RVD)) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
+ }
+ }
+}
+
static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
{
RISCVCPUImpliedExtsRule *rule;
int i;
+ /* Enable the implied extensions for Zc. */
+ cpu_enable_zc_implied_rules(cpu);
+
/* Enable the implied MISAs. */
for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
if (riscv_has_ext(&cpu->env, rule->ext)) {
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH RESEND 6/6] target/riscv: Remove extension auto-update check statements
2024-06-05 6:31 [PATCH RESEND 0/6] Introduce extension implied rules frank.chang
` (4 preceding siblings ...)
2024-06-05 6:31 ` [PATCH RESEND 5/6] target/riscv: Add Zc extension implied rule frank.chang
@ 2024-06-05 6:31 ` frank.chang
2024-06-05 7:48 ` [PATCH RESEND 0/6] Introduce extension implied rules Jerry Zhang Jian
6 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2024-06-05 6:31 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/tcg/tcg-cpu.c | 115 -------------------------------------
1 file changed, 115 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ed10ac799a..c1926db370 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -469,10 +469,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_zfh) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
- }
-
if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
@@ -494,9 +490,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_propagate(errp, local_err);
return;
}
-
- /* The V vector extension depends on the Zve64d extension */
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
}
/* The Zve64d extension depends on the Zve64f extension */
@@ -505,18 +498,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_setg(errp, "Zve64d/V extensions require D extension");
return;
}
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
- }
-
- /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
- if (cpu->cfg.ext_zve64f) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
- }
-
- /* The Zve64x extension depends on the Zve32x extension */
- if (cpu->cfg.ext_zve64x) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
}
/* The Zve32f extension depends on the Zve32x extension */
@@ -525,11 +506,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
- }
-
- if (cpu->cfg.ext_zvfh) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
}
if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
@@ -552,11 +528,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- /* Set the ISA extensions, checks should have happened above */
- if (cpu->cfg.ext_zhinx) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- }
-
if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
return;
@@ -574,27 +545,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
- if (cpu->cfg.ext_zce) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
- if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
- }
- }
-
- /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
- if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
- }
- if (riscv_has_ext(env, RVD)) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
- }
- }
-
if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
error_setg(errp, "Zcf extension is only relevant to RV32");
return;
@@ -628,48 +578,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- /*
- * Shorthand vector crypto extensions
- */
- if (cpu->cfg.ext_zvknc) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
- }
-
- if (cpu->cfg.ext_zvkng) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
- }
-
- if (cpu->cfg.ext_zvkn) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
- }
-
- if (cpu->cfg.ext_zvksc) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
- }
-
- if (cpu->cfg.ext_zvksg) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
- }
-
- if (cpu->cfg.ext_zvks) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
- }
-
- if (cpu->cfg.ext_zvkt) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
- }
-
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
@@ -685,29 +593,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_zk) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
- }
-
- if (cpu->cfg.ext_zkn) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
- }
-
- if (cpu->cfg.ext_zks) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
- }
-
if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) {
if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) {
error_setg(errp, "zicntr requires zicsr");
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH RESEND 0/6] Introduce extension implied rules
2024-06-05 6:31 [PATCH RESEND 0/6] Introduce extension implied rules frank.chang
` (5 preceding siblings ...)
2024-06-05 6:31 ` [PATCH RESEND 6/6] target/riscv: Remove extension auto-update check statements frank.chang
@ 2024-06-05 7:48 ` Jerry Zhang Jian
6 siblings, 0 replies; 13+ messages in thread
From: Jerry Zhang Jian @ 2024-06-05 7:48 UTC (permalink / raw)
To: alistair.francis, palmer, frank.chang, bmeng.cn, liwei1518,
dbarboza, zhiwei_liu, qemu-devel, qemu-riscv
Cc: Jerry Zhang Jian
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
--
2.44.0
^ permalink raw reply [flat|nested] 13+ messages in thread