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Mon, 13 Oct 2025 22:08:11 -0700 (PDT) MIME-Version: 1.0 References: <20251010155045.78220-1-philmd@linaro.org> <20251010155045.78220-10-philmd@linaro.org> In-Reply-To: <20251010155045.78220-10-philmd@linaro.org> From: Alistair Francis Date: Tue, 14 Oct 2025 15:07:45 +1000 X-Gm-Features: AS18NWAC0HmOkOTJ_8CJMIHcP-auKC22syij_2RnEY6lDjNh_h3nQWeH1pOpEII Message-ID: Subject: Re: [PATCH 09/13] target/riscv: Conceal MO_TE within gen_cmpxchg*() To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Christoph Muellner , Heinrich Schuchardt , Palmer Dabbelt , Alistair Francis , Liu Zhiwei , Anton Johansson , Richard Henderson , Valentin Haudiquet , Weiwei Li , qemu-riscv@nongnu.org, Daniel Henrique Barboza Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sat, Oct 11, 2025 at 1:55=E2=80=AFAM Philippe Mathieu-Daud=C3=A9 wrote: > > All callers of gen_cmpxchg() / gen_cmpxchg64() set the MO_TE flag. > Set it once in the callees. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c | 1 + > target/riscv/insn_trans/trans_rvzabha.c.inc | 2 +- > target/riscv/insn_trans/trans_rvzacas.c.inc | 7 ++++--- > 3 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 94af9853cfe..2e6f39aa02d 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1156,6 +1156,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atom= ic *a, MemOp mop) > TCGv src1 =3D get_address(ctx, a->rs1, 0); > TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); > > + mop |=3D MO_TE; > decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); > tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop)= ; > > diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/i= nsn_trans/trans_rvzabha.c.inc > index c1f99b65f09..302c63f2a3d 100644 > --- a/target/riscv/insn_trans/trans_rvzabha.c.inc > +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc > @@ -141,5 +141,5 @@ static bool trans_amocas_h(DisasContext *ctx, arg_amo= cas_h *a) > { > REQUIRE_ZACAS(ctx); > REQUIRE_ZABHA(ctx); > - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SW); > + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_SW); > } > diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/i= nsn_trans/trans_rvzacas.c.inc > index 5e7c7c92b72..d850b142642 100644 > --- a/target/riscv/insn_trans/trans_rvzacas.c.inc > +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc > @@ -25,7 +25,7 @@ > static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a) > { > REQUIRE_ZACAS(ctx); > - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SL); > + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_SL); > } > > static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num) > @@ -76,6 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic= *a, MemOp mop) > TCGv src1 =3D get_address(ctx, a->rs1, 0); > TCGv_i64 src2 =3D get_gpr_pair(ctx, a->rs2); > > + mop |=3D MO_TE; > decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); > tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop= ); > > @@ -88,10 +89,10 @@ static bool trans_amocas_d(DisasContext *ctx, arg_amo= cas_d *a) > REQUIRE_ZACAS(ctx); > switch (get_ol(ctx)) { > case MXL_RV32: > - return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_TE | MO_UQ); > + return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_UQ); > case MXL_RV64: > case MXL_RV128: > - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_UQ); > + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_UQ); > default: > g_assert_not_reached(); > } > -- > 2.51.0 > >