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Wed, 30 Jul 2025 21:37:09 -0700 (PDT) MIME-Version: 1.0 References: <20250730010122.4193496-1-alistair.francis@wdc.com> In-Reply-To: From: Alistair Francis Date: Thu, 31 Jul 2025 14:36:43 +1000 X-Gm-Features: Ac12FXwlmJhFkYCYUbKiswsoM6mxS70S3XagKYH4e03beRx_LG5WTqeu1dWvp0A Message-ID: Subject: Re: [PULL 00/11] riscv-to-apply queue To: Michael Tokarev Cc: qemu-devel@nongnu.org, Alistair Francis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2f; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jul 31, 2025 at 4:20=E2=80=AFAM Michael Tokarev wr= ote: > > On 30.07.2025 04:01, alistair23@gmail.com wrote: > > From: Alistair Francis > > > > The following changes since commit 9b80226ece693197af8a981b424391b68b5b= c38e: > > > > Update version for the v10.1.0-rc1 release (2025-07-29 13:00:41 -040= 0) > > > > are available in the Git repository at: > > > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-2025= 0730-2 > > > > for you to fetch changes up to 86bc3a0abf10072081cddd8dff25aa72c60e67b8= : > > > > target/riscv: Restrict midelegh access to S-mode harts (2025-07-30 1= 0:59:26 +1000) > > > > ---------------------------------------------------------------- > > Third RISC-V PR for 10.1 > > > > * Fix pmp range wraparound on zero > > * Update FADT and MADT versions in ACPI tables > > * Fix target register read when source is inactive > > * Add riscv_hwprobe entry to linux-user strace list > > * Do not call GETPC() in check_ret_from_m_mode() > > * Revert "Generate strided vector loads/stores with tcg nodes." > > * Fix exception type when VU accesses supervisor CSRs > > * Restrict mideleg/medeleg/medelegh access to S-mode harts > > * Restrict midelegh access to S-mode harts > > > > ---------------------------------------------------------------- > > Daniel Henrique Barboza (3): > > linux-user/strace.list: add riscv_hwprobe entry > > target/riscv: do not call GETPC() in check_ret_from_m_mode() > > riscv: Revert "Generate strided vector loads/stores with tcg nod= es." > > > > Jay Chang (2): > > target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode= harts > > target/riscv: Restrict midelegh access to S-mode harts > > > > Sunil V L (3): > > bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT chan= ges > > hw/riscv/virt-acpi-build.c: Update FADT and MADT versions > > tests/data/acpi/riscv64: Update expected FADT and MADT > > > > Vac Chen (1): > > target/riscv: Fix pmp range wraparound on zero > > > > Xu Lu (1): > > target/riscv: Fix exception type when VU accesses supervisor CSR= s > > > > Yang Jialong (1): > > intc/riscv_aplic: Fix target register read when source is inacti= ve > > Is there anything there for qemu-stable? Urgh, sorry I forgot to CC qemu-stable. > > It looks like "Fix exception type when VU accesses supervisor CSRs" is a > good candidate, maybe "Fix pmp range wraparound on zero" too. Something > else? "Fix target register read when source is inactive"? The "S-mode > harts" ones? > > I already picked up "do not call GETPC()" as it's been Cc'd qemu-stable > before, and I'm picking up riscv_hwprobe too, as it's trivial and fixes > a trivial omission which might be useful. Should I pick up others I > mentioned? Thanks for getting those two 77707bfdf8 target/riscv: Fix pmp range wraparound on zero b6f1244678 intc/riscv_aplic: Fix target register read when source is inacti= ve 30ef718423 target/riscv: Fix exception type when VU accesses supervisor CSR= s e443ba0336 target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts 86bc3a0abf target/riscv: Restrict midelegh access to S-mode harts Are all good candidates for back porting as well Alistair > > Thanks, > > /mjt