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From: Alistair Francis <alistair23@gmail.com>
Date: Wed, 23 May 2018 15:56:53 -0700
Message-ID: <CAKmqyKNHERg+twEx+LvJ_TFdtnBGTW288ZvLB5YuJs9CHVQSKQ@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize
 setting of PVR11_USE_MMU
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To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Edgar Iglesias <edgar.iglesias@xilinx.com>, Peter Maydell <peter.maydell@linaro.org>, Stefano Stabellini <sstabellini@kernel.org>, Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>, Francisco Iglesias <frasse.iglesias@gmail.com>, Alistair Francis <alistair@alistair23.me>, Richard Henderson <richard.henderson@linaro.org>, KONRAD Frederic <frederic.konrad@adacore.com>

On Wed, May 23, 2018 at 3:47 PM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Conditionalize setting of PVR11_USE_MMU on the use_mmu
> CPU property, otherwise we may incorrectly advertise an
> MMU via PVR when the core in fact has none.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/microblaze/cpu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 06476f6efc..a6f1ce6549 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -201,7 +201,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                                          PVR5_DCACHE_WRITEBACK_MASK : 0;
>
>      env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
> -    env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
> +    env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
> +                        16 << 17;
>
>      mcc->parent_realize(dev, errp);
>  }
> --
> 2.14.1
>
>