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Wed, 25 Mar 2026 19:06:34 -0700 (PDT) MIME-Version: 1.0 References: <20260318103122.97244-1-philmd@linaro.org> <20260318103122.97244-4-philmd@linaro.org> In-Reply-To: <20260318103122.97244-4-philmd@linaro.org> From: Alistair Francis Date: Thu, 26 Mar 2026 12:06:08 +1000 X-Gm-Features: AQROBzBK9UvDAX6qerJ0r_r0-FIKhiMxPmcMjWfNegpd7VqVcdbHLqKQx0pRvas Message-ID: Subject: Re: [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Weiwei Li , Pierrick Bouvier , Warner Losh , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , Vijai Kumar K , Anton Johansson , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Jiaxun Yang , Peter Maydell , Liu Zhiwei , Djordje Todorovic , Richard Henderson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 18, 2026 at 8:34=E2=80=AFPM Philippe Mathieu-Daud=C3=A9 wrote: > > From: Fr=C3=A9d=C3=A9ric P=C3=A9trot > > The lq and sq helpers for the experimental rv128 architecture > currently use direct memory accesses. > Replace these direct accesses with the standard > tcg_gen_qemu_{ld,st}_i128 TCG helpers that handle endianness > issues. > > Reported-by: Philippe Mathieu-Daud=C3=A9 > Suggested-by: Richard Henderson > Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot > Message-ID: <20260101181442.2489496-2-frederic.petrot@univ-grenoble-alpes= .fr> > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvi.c.inc | 32 ++++++++++++++++++------- > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_= trans/trans_rvi.c.inc > index 54b9b4f2413..2c82ae41a77 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -377,6 +377,9 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *= a, MemOp memop) > TCGv destl =3D dest_gpr(ctx, a->rd); > TCGv desth =3D dest_gprh(ctx, a->rd); > TCGv addrl =3D tcg_temp_new(); > + TCGv_i128 t16 =3D tcg_temp_new_i128(); > + TCGv_i64 tl =3D tcg_temp_new_i64(); > + TCGv_i64 th =3D tcg_temp_new_i64(); > > tcg_gen_addi_tl(addrl, src1l, a->imm); > > @@ -388,10 +391,14 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb= *a, MemOp memop) > tcg_gen_movi_tl(desth, 0); > } > } else { > - /* assume little-endian memory access for now */ > - tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, MO_TEUQ); > - tcg_gen_addi_tl(addrl, addrl, 8); > - tcg_gen_qemu_ld_tl(desth, addrl, ctx->mem_idx, MO_TEUQ); > + tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop); > + if (mo_endian(ctx) =3D=3D MO_LE) { > + tcg_gen_extr_i128_i64(tl, th, t16); > + } else { > + tcg_gen_extr_i128_i64(th, tl, t16); > + } > + tcg_gen_trunc_i64_tl(destl, tl); > + tcg_gen_trunc_i64_tl(desth, th); > } > > gen_set_gpr128(ctx, a->rd, destl, desth); > @@ -488,16 +495,25 @@ static bool gen_store_i128(DisasContext *ctx, arg_s= b *a, MemOp memop) > TCGv src2l =3D get_gpr(ctx, a->rs2, EXT_NONE); > TCGv src2h =3D get_gprh(ctx, a->rs2); > TCGv addrl =3D tcg_temp_new(); > + TCGv_i128 t16 =3D tcg_temp_new_i128(); > + TCGv_i64 tl =3D tcg_temp_new_i64(); > + TCGv_i64 th =3D tcg_temp_new_i64(); > > tcg_gen_addi_tl(addrl, src1l, a->imm); > > if ((memop & MO_SIZE) <=3D MO_64) { > tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop); > } else { > - /* little-endian memory access assumed for now */ > - tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, MO_TEUQ); > - tcg_gen_addi_tl(addrl, addrl, 8); > - tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ); > + > + tcg_gen_ext_tl_i64(tl, src2l); > + tcg_gen_ext_tl_i64(th, src2h); > + > + if (mo_endian(ctx) =3D=3D MO_LE) { > + tcg_gen_concat_i64_i128(t16, tl, th); > + } else { > + tcg_gen_concat_i64_i128(t16, th, tl); > + } > + tcg_gen_qemu_st_i128(t16, addrl, ctx->mem_idx, memop); > } > return true; > } > -- > 2.53.0 > >