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Wed, 04 May 2022 01:59:19 -0700 (PDT) MIME-Version: 1.0 References: <20220503194843.1379101-1-richard.henderson@linaro.org> <20220503194843.1379101-17-richard.henderson@linaro.org> In-Reply-To: <20220503194843.1379101-17-richard.henderson@linaro.org> From: Alistair Francis Date: Wed, 4 May 2022 18:58:53 +1000 Message-ID: Subject: Re: [PATCH v2 16/74] semihosting: Split is_64bit_semihosting per target To: Richard Henderson Cc: "qemu-devel@nongnu.org Developers" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::136; envelope-from=alistair23@gmail.com; helo=mail-il1-x136.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, May 4, 2022 at 6:11 AM Richard Henderson wrote: > > We already have some larger ifdef blocks for ARM and RISCV; > split the function into multiple implementations per arch. > > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > semihosting/arm-compat-semi.c | 19 ++++++++----------- > 1 file changed, 8 insertions(+), 11 deletions(-) > > diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c > index a6c6e5baf6..7fc60e223a 100644 > --- a/semihosting/arm-compat-semi.c > +++ b/semihosting/arm-compat-semi.c > @@ -213,6 +213,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) > return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); > } > > +static inline bool is_64bit_semihosting(CPUArchState *env) > +{ > + return is_a64(env); > +} > #endif /* TARGET_ARM */ > > #ifdef TARGET_RISCV > @@ -238,6 +242,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) > return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); > } > > +static inline bool is_64bit_semihosting(CPUArchState *env) > +{ > + return riscv_cpu_mxl(env) != MXL_RV32; > +} > #endif > > /* > @@ -586,17 +594,6 @@ static const GuestFDFunctions guestfd_fns[] = { > * call if the memory read fails. Eventually we could use a generic > * CPUState helper function here. > */ > -static inline bool is_64bit_semihosting(CPUArchState *env) > -{ > -#if defined(TARGET_ARM) > - return is_a64(env); > -#elif defined(TARGET_RISCV) > - return riscv_cpu_mxl(env) != MXL_RV32; > -#else > -#error un-handled architecture > -#endif > -} > - > > #define GET_ARG(n) do { \ > if (is_64bit_semihosting(env)) { \ > -- > 2.34.1 > >