From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Alistair Francis <alistair.francis@opensource.wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency
Date: Tue, 21 Dec 2021 16:32:23 +1000 [thread overview]
Message-ID: <CAKmqyKNLZGD-81xnFp_NMXKRuK-0EgP4FqW4AeLeKuMD+TAQEw@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmVpGwjqvhLN1LCY3EokL9_a_v9okL=ZwUb_JYMZcvv3zw@mail.gmail.com>
On Mon, Dec 20, 2021 at 5:52 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > As per the device tree specification let's set the clock-frequency for
> > the virt CPUs.
> >
> > QEMU doesn't really have an exact clock, so let's just 1000000 as it's a
> > nice round number and matches the sifive_u CLINT_TIMEBASE_FREQ.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/472 (RISC-V virt)
>
> I tend to think this issue is not valid, as the comment in the issue
> says the value should reflect the running frequency.
>
> Note the "clock-frequency" was once in the codes but was intentionally
> removed before because it is not needed:
>
> See commit 7ae05377b85f (" riscv: hw: Drop "clock-frequency" property
> of cpu nodes")
Hmmm... Good point.
But if the device tree spec says it's required then I think we should
include it. Even if it isn't super relevant for us
Alistair
>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/virt.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 3af074148e..41a85cfc60 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -202,6 +202,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
> > qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
> > s->soc[socket].hartid_base + cpu);
> > qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
> > + qemu_fdt_setprop_cell(mc->fdt, cpu_name, "clock-frequency", 1000000);
> > riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
> > qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
>
> Regards,
> Bin
next prev parent reply other threads:[~2021-12-21 6:35 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 4:54 [PATCH v2 0/9] A collection of RISC-V cleanups and improvements Alistair Francis
2021-12-16 4:54 ` [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function Alistair Francis
2021-12-16 8:16 ` Philippe Mathieu-Daudé
2021-12-21 8:00 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-12-21 8:22 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2021-12-16 5:59 ` Anup Patel
2021-12-20 2:52 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 2:53 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2021-12-20 7:38 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2021-12-16 5:58 ` Anup Patel
2021-12-16 8:18 ` Philippe Mathieu-Daudé
2021-12-20 5:41 ` Alistair Francis
2021-12-20 7:39 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 7:51 ` Bin Meng
2021-12-21 6:32 ` Alistair Francis [this message]
2021-12-21 6:56 ` Bin Meng
2022-02-22 15:41 ` Peter Maydell
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