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Tue, 06 Dec 2022 20:31:46 -0800 (PST) MIME-Version: 1.0 References: <20221201140811.142123-1-bmeng@tinylab.org> <20221201140811.142123-10-bmeng@tinylab.org> In-Reply-To: <20221201140811.142123-10-bmeng@tinylab.org> From: Alistair Francis Date: Wed, 7 Dec 2022 14:31:19 +1000 Message-ID: Subject: Re: [PATCH 10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC To: Bin Meng Cc: Alistair Francis , qemu-devel@nongnu.org, Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a34; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Dec 2, 2022 at 12:12 AM Bin Meng wrote: > > Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003 > supports 52 interrupt sources while G000 supports 51 interrupt sources. > > We use the value of G002 and G003, so it is 53 (including source 0). > > [1] G000 manual: > https://sifive.cdn.prismic.io/sifive/4faf3e34-4a42-4c2f-be9e-c77baa4928c7_fe310-g000-manual-v3p2.pdf > > [2] G002 manual: > https://sifive.cdn.prismic.io/sifive/034760b5-ac6a-4b1c-911c-f4148bb2c4a5_fe310-g002-v1p5.pdf > > [3] G003 manual: > https://sifive.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf > > Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine") > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > include/hw/riscv/sifive_e.h | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h > index d738745925..9e58247fd8 100644 > --- a/include/hw/riscv/sifive_e.h > +++ b/include/hw/riscv/sifive_e.h > @@ -82,7 +82,12 @@ enum { > }; > > #define SIFIVE_E_PLIC_HART_CONFIG "M" > -#define SIFIVE_E_PLIC_NUM_SOURCES 127 > +/* > + * Freedom E310 G002 and G003 supports 52 interrupt sources while > + * Freedom E310 G000 supports 51 interrupt sources. We use the value > + * of G002 and G003, so it is 53 (including interrupt source 0). > + */ > +#define SIFIVE_E_PLIC_NUM_SOURCES 53 > #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 > #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 > #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 > -- > 2.34.1 > >