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From: Alistair Francis <alistair23@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>
Cc: Richard Henderson <richard.henderson@linaro.org>,
	Kito Cheng <kito.cheng@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v6 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Date: Mon, 30 Aug 2021 14:44:37 +1000	[thread overview]
Message-ID: <CAKmqyKNM75orG9KvGeuiMEQA-xvdcuTgq+3hs8XDot70aODniw@mail.gmail.com> (raw)
In-Reply-To: <20210825165907.34026-2-philipp.tomsich@vrull.eu>

On Thu, Aug 26, 2021 at 3:01 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> The bitmanipulation ISA extensions will be ratified as individual
> small extension packages instead of a large B-extension.  The first
> new instructions through the door (these have completed public review)
> are Zb[abcs].
>
> This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
> these in target/riscv/cpu.[ch].
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Split off removal of 'x-b' property and 'ext_b' field into a separate
>   patch to ensure bisectability.
>
>  target/riscv/cpu.c | 4 ++++
>  target/riscv/cpu.h | 4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 991a6bb760..c7bc1f9f44 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -585,6 +585,10 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      /* This is experimental so mark with 'x-' */
>      DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
> +    DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
> +    DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
> +    DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
> +    DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bf1c899c00..7c4cd8ea89 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -293,6 +293,10 @@ struct RISCVCPU {
>          bool ext_u;
>          bool ext_h;
>          bool ext_v;
> +        bool ext_zba;
> +        bool ext_zbb;
> +        bool ext_zbc;
> +        bool ext_zbs;
>          bool ext_counters;
>          bool ext_ifencei;
>          bool ext_icsr;
> --
> 2.25.1
>
>


  reply	other threads:[~2021-08-30  4:46 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-25 16:58 [PATCH v6 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-08-25 16:58 ` [PATCH v6 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-08-30  4:44   ` Alistair Francis [this message]
2021-08-25 16:58 ` [PATCH v6 02/14] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-08-30  4:45   ` Alistair Francis
2021-08-25 16:58 ` [PATCH v6 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits Philipp Tomsich
2021-08-30  4:46   ` Alistair Francis
2021-08-25 16:58 ` [PATCH v6 04/14] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-08-30  4:48   ` Alistair Francis
2021-08-25 16:58 ` [PATCH v6 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-08-30  4:49   ` Alistair Francis
2021-08-25 16:58 ` [PATCH v6 06/14] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-08-30  4:50   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 07/14] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-08-30  5:11   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 08/14] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-08-30  5:12   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-08-30  5:15   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-08-30  5:16   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 11/14] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-08-30  5:18   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-08-30  5:23   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 13/14] target/riscv: Remove RVB (replaced by Zb[abcs] Philipp Tomsich
2021-08-30  5:24   ` Alistair Francis
2021-08-25 16:59 ` [PATCH v6 14/14] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich

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