* [PATCH v1 1/1] target/riscv: Update the ePMP CSR address
@ 2021-09-02 0:40 Alistair Francis
2021-09-02 1:57 ` Bin Meng
0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2021-09-02 0:40 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair.francis, alistair23
From: Alistair Francis <alistair.francis@wdc.com>
Update the ePMP CSRs to match the 0.9.3 ePMP spec
https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 4 ++--
target/riscv/cpu.c | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7330ff5a19..ce9dcc030c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -210,8 +210,8 @@
#define CSR_MTVAL2 0x34b
/* Enhanced Physical Memory Protection (ePMP) */
-#define CSR_MSECCFG 0x390
-#define CSR_MSECCFGH 0x391
+#define CSR_MSECCFG 0x747
+#define CSR_MSECCFGH 0x757
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a2b03d579..8ecb8df780 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -599,6 +599,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ /* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v1 1/1] target/riscv: Update the ePMP CSR address
2021-09-02 0:40 [PATCH v1 1/1] target/riscv: Update the ePMP CSR address Alistair Francis
@ 2021-09-02 1:57 ` Bin Meng
2021-09-02 5:19 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: Bin Meng @ 2021-09-02 1:57 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Thu, Sep 2, 2021 at 8:40 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Update the ePMP CSRs to match the 0.9.3 ePMP spec
> https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu_bits.h | 4 ++--
> target/riscv/cpu.c | 1 +
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1 1/1] target/riscv: Update the ePMP CSR address
2021-09-02 1:57 ` Bin Meng
@ 2021-09-02 5:19 ` Alistair Francis
0 siblings, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-09-02 5:19 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Alistair Francis, Palmer Dabbelt,
Alistair Francis, qemu-devel@nongnu.org Developers
On Thu, Sep 2, 2021 at 11:57 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Thu, Sep 2, 2021 at 8:40 AM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > Update the ePMP CSRs to match the 0.9.3 ePMP spec
> > https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/cpu_bits.h | 4 ++--
> > target/riscv/cpu.c | 1 +
> > 2 files changed, 3 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-09-02 0:40 [PATCH v1 1/1] target/riscv: Update the ePMP CSR address Alistair Francis
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