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Sun, 23 Feb 2025 18:55:31 -0800 (PST) MIME-Version: 1.0 References: <20241205133003.184581-1-dbarboza@ventanamicro.com> <20241205133003.184581-6-dbarboza@ventanamicro.com> In-Reply-To: <20241205133003.184581-6-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 24 Feb 2025 12:55:05 +1000 X-Gm-Features: AWEUYZkF_QMGkHsfRW7FVshj3iL1UuMvv2oOHVSww3fVDAektx2D7nTf-oWy8qY Message-ID: Subject: Re: [PATCH for-10.0 05/11] hw/riscv/riscv-iommu: instantiate hpm_timer To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Tomasz Jeznach Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2e; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Dec 5, 2024 at 11:35=E2=80=AFPM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > The next HPM related changes requires the HPM overflow timer to be > initialized by the riscv-iommu base emulation. > > Signed-off-by: Tomasz Jeznach > Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > hw/riscv/riscv-iommu-hpm.c | 36 ++++++++++++++++++++++++++++++++++++ > hw/riscv/riscv-iommu-hpm.h | 1 + > hw/riscv/riscv-iommu.c | 3 +++ > hw/riscv/riscv-iommu.h | 2 ++ > 4 files changed, 42 insertions(+) > > diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c > index 8eca5ee17e..325088333e 100644 > --- a/hw/riscv/riscv-iommu-hpm.c > +++ b/hw/riscv/riscv-iommu-hpm.c > @@ -166,3 +166,39 @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RI= SCVIOMMUContext *ctx, > hpm_incr_ctr(s, ctr_idx); > } > } > + > +/* Timer callback for cycle counter overflow. */ > +void riscv_iommu_hpm_timer_cb(void *priv) > +{ > + RISCVIOMMUState *s =3D priv; > + const uint32_t inhibit =3D riscv_iommu_reg_get32( > + s, RISCV_IOMMU_REG_IOCOUNTINH); > + uint32_t ovf; > + > + if (get_field(inhibit, RISCV_IOMMU_IOCOUNTINH_CY)) { > + return; > + } > + > + if (s->irq_overflow_left > 0) { > + uint64_t irq_trigger_at =3D > + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->irq_overflow_left= ; > + timer_mod_anticipate_ns(s->hpm_timer, irq_trigger_at); > + s->irq_overflow_left =3D 0; > + return; > + } > + > + ovf =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF); > + if (!get_field(ovf, RISCV_IOMMU_IOCOUNTOVF_CY)) { > + /* > + * We don't need to set hpmcycle_val to zero and update hpmcycle= _prev to > + * current clock value. The way we calculate iohpmcycs will over= flow > + * and return the correct value. This avoids the need to synchro= nize > + * timer callback and write callback. > + */ > + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF, > + RISCV_IOMMU_IOCOUNTOVF_CY, 0); > + riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_IOHPMCYCLES, > + RISCV_IOMMU_IOHPMCYCLES_OVF, 0); > + riscv_iommu_notify(s, RISCV_IOMMU_INTR_PM); > + } > +} > diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h > index 411d869dce..cd896d3b7c 100644 > --- a/hw/riscv/riscv-iommu-hpm.h > +++ b/hw/riscv/riscv-iommu-hpm.h > @@ -25,5 +25,6 @@ > uint64_t riscv_iommu_hpmcycle_read(RISCVIOMMUState *s); > void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx= , > unsigned event_id); > +void riscv_iommu_hpm_timer_cb(void *priv); > > #endif > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index 5ce0d24359..2ec388ff3d 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -2281,6 +2281,8 @@ static void riscv_iommu_realize(DeviceState *dev, E= rror **errp) > address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as"); > > if (s->cap & RISCV_IOMMU_CAP_HPM) { > + s->hpm_timer =3D > + timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_iommu_hpm_timer_cb, s= ); > s->hpm_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direc= t_equal); > } > } > @@ -2294,6 +2296,7 @@ static void riscv_iommu_unrealize(DeviceState *dev) > > if (s->cap & RISCV_IOMMU_CAP_HPM) { > g_hash_table_unref(s->hpm_event_ctr_map); > + timer_free(s->hpm_timer); > } > } > > diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h > index a21ab51491..6ddc59f474 100644 > --- a/hw/riscv/riscv-iommu.h > +++ b/hw/riscv/riscv-iommu.h > @@ -88,8 +88,10 @@ struct RISCVIOMMUState { > QLIST_HEAD(, RISCVIOMMUSpace) spaces; > > /* HPM cycle counter */ > + QEMUTimer *hpm_timer; > uint64_t hpmcycle_val; /* Current value of cycle register */ > uint64_t hpmcycle_prev; /* Saved value of QEMU_CLOCK_VIRTUAL clo= ck */ > + uint64_t irq_overflow_left; /* Value beyond INT64_MAX after overflow= */ > > /* HPM event counters */ > GHashTable *hpm_event_ctr_map; /* Mapping of events to counters */ > -- > 2.47.1 > >