From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com, richard.henderson@linaro.org,
max.chou@sifive.com
Subject: Re: [PATCH v6 5/9] target/riscv: remove 'cpu_vl' global
Date: Wed, 6 Mar 2024 11:32:26 +1000 [thread overview]
Message-ID: <CAKmqyKNOoxZ1gUr4Jd9nhV_x7T8ONDFTdB58F1iyRu3_CGbnEw@mail.gmail.com> (raw)
In-Reply-To: <20240221213140.365232-6-dbarboza@ventanamicro.com>
On Thu, Feb 22, 2024 at 7:34 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> At this moment the global is used only in do_vsetvl(). Do a direct env
> load in do_vsetvl() to read 'vl' and remove the global.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
> target/riscv/translate.c | 3 +--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 58299d9bb8..69f32d081e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -157,7 +157,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
>
> if (rd == 0 && rs1 == 0) {
> s1 = tcg_temp_new();
> - tcg_gen_mov_tl(s1, cpu_vl);
> + tcg_gen_ld_tl(s1, tcg_env, offsetof(CPURISCVState, vl));
> } else if (rs1 == 0) {
> /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> s1 = tcg_constant_tl(RV_VLEN_MAX);
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f2f0593830..3040f5e0e4 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -38,7 +38,7 @@
> #undef HELPER_H
>
> /* global register indices */
> -static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
> +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc;
> static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> static TCGv load_res;
> static TCGv load_val;
> @@ -1320,7 +1320,6 @@ void riscv_translate_init(void)
> }
>
> cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
> - cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
> load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
> "load_res");
> load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
> --
> 2.43.2
>
>
next prev parent reply other threads:[~2024-03-06 1:33 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-21 21:31 [PATCH v6 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
2024-02-21 21:31 ` [PATCH v6 1/9] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Daniel Henrique Barboza
2024-03-06 1:22 ` Alistair Francis
2024-02-21 21:31 ` [PATCH v6 2/9] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Daniel Henrique Barboza
2024-03-06 1:25 ` Alistair Francis
2024-02-21 21:31 ` [PATCH v6 3/9] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
2024-03-06 1:27 ` Alistair Francis
2024-02-21 21:31 ` [PATCH v6 4/9] target/riscv/translate.c: remove 'cpu_vstart' global Daniel Henrique Barboza
2024-02-22 7:59 ` Philippe Mathieu-Daudé
2024-03-06 1:28 ` Alistair Francis
2024-02-21 21:31 ` [PATCH v6 5/9] target/riscv: remove 'cpu_vl' global Daniel Henrique Barboza
2024-02-21 22:01 ` Richard Henderson
2024-02-22 7:59 ` Philippe Mathieu-Daudé
2024-03-06 1:32 ` Alistair Francis [this message]
2024-02-21 21:31 ` [PATCH v6 6/9] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
2024-03-06 1:35 ` Alistair Francis
2024-02-21 21:31 ` [PATCH v6 7/9] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
2024-03-06 1:36 ` Alistair Francis
2024-02-21 21:31 ` [PATCH v6 8/9] target/riscv: Clear vstart_qe_zero flag Daniel Henrique Barboza
2024-03-06 1:38 ` Alistair Francis
2024-02-21 21:31 ` [PATCH v6 9/9] target/riscv/vector_helper.c: optimize loops in ldst helpers Daniel Henrique Barboza
2024-02-21 22:03 ` Richard Henderson
2024-03-06 1:39 ` Alistair Francis
2024-03-06 1:58 ` [PATCH v6 0/9] riscv: set vstart_eq_zero on mark_vs_dirty Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAKmqyKNOoxZ1gUr4Jd9nhV_x7T8ONDFTdB58F1iyRu3_CGbnEw@mail.gmail.com \
--to=alistair23@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=max.chou@sifive.com \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).