Re: [PATCH for-10.0 02/11] hw/riscv/riscv-iommu-bits.h: HPM bits

[Alistair Francis <alistair23@gmail.com>]

On Thu, Dec 5, 2024 at 11:33 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> From: Tomasz Jeznach <tjeznach@rivosinc.com>
>
> Add the relevant HPM (High Performance Monitor) bits that we'll be using
> in the next patches.
>
> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/riscv-iommu-bits.h | 47 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
> index 485f36b9c9..298a060085 100644
> --- a/hw/riscv/riscv-iommu-bits.h
> +++ b/hw/riscv/riscv-iommu-bits.h
> @@ -82,6 +82,7 @@ struct riscv_iommu_pq_record {
>  #define RISCV_IOMMU_CAP_ATS             BIT_ULL(25)
>  #define RISCV_IOMMU_CAP_T2GPA           BIT_ULL(26)
>  #define RISCV_IOMMU_CAP_IGS             GENMASK_ULL(29, 28)
> +#define RISCV_IOMMU_CAP_HPM             BIT_ULL(30)
>  #define RISCV_IOMMU_CAP_DBG             BIT_ULL(31)
>  #define RISCV_IOMMU_CAP_PAS             GENMASK_ULL(37, 32)
>  #define RISCV_IOMMU_CAP_PD8             BIT_ULL(38)
> @@ -191,6 +192,52 @@ enum {
>      RISCV_IOMMU_INTR_COUNT
>  };
>
> +#define RISCV_IOMMU_IOCOUNT_NUM         31
> +
> +/* 5.19 Performance monitoring counter overflow status (32bits) */
> +#define RISCV_IOMMU_REG_IOCOUNTOVF      0x0058
> +#define RISCV_IOMMU_IOCOUNTOVF_CY       BIT(0)
> +
> +/* 5.20 Performance monitoring counter inhibits (32bits) */
> +#define RISCV_IOMMU_REG_IOCOUNTINH      0x005C
> +#define RISCV_IOMMU_IOCOUNTINH_CY       BIT(0)
> +
> +/* 5.21 Performance monitoring cycles counter (64bits) */
> +#define RISCV_IOMMU_REG_IOHPMCYCLES     0x0060
> +#define RISCV_IOMMU_IOHPMCYCLES_COUNTER GENMASK_ULL(62, 0)
> +#define RISCV_IOMMU_IOHPMCYCLES_OVF     BIT_ULL(63)
> +
> +/* 5.22 Performance monitoring event counters (31 * 64bits) */
> +#define RISCV_IOMMU_REG_IOHPMCTR_BASE   0x0068
> +#define RISCV_IOMMU_REG_IOHPMCTR(_n)    \
> +    (RISCV_IOMMU_REG_IOHPMCTR_BASE + (_n * 0x8))
> +
> +/* 5.23 Performance monitoring event selectors (31 * 64bits) */
> +#define RISCV_IOMMU_REG_IOHPMEVT_BASE   0x0160
> +#define RISCV_IOMMU_REG_IOHPMEVT(_n)    \
> +    (RISCV_IOMMU_REG_IOHPMEVT_BASE + (_n * 0x8))
> +#define RISCV_IOMMU_IOHPMEVT_EVENT_ID   GENMASK_ULL(14, 0)
> +#define RISCV_IOMMU_IOHPMEVT_DMASK      BIT_ULL(15)
> +#define RISCV_IOMMU_IOHPMEVT_PID_PSCID  GENMASK_ULL(35, 16)
> +#define RISCV_IOMMU_IOHPMEVT_DID_GSCID  GENMASK_ULL(59, 36)
> +#define RISCV_IOMMU_IOHPMEVT_PV_PSCV    BIT_ULL(60)
> +#define RISCV_IOMMU_IOHPMEVT_DV_GSCV    BIT_ULL(61)
> +#define RISCV_IOMMU_IOHPMEVT_IDT        BIT_ULL(62)
> +#define RISCV_IOMMU_IOHPMEVT_OF         BIT_ULL(63)
> +
> +enum RISCV_IOMMU_HPMEVENT_id {
> +    RISCV_IOMMU_HPMEVENT_INVALID    = 0,
> +    RISCV_IOMMU_HPMEVENT_URQ        = 1,
> +    RISCV_IOMMU_HPMEVENT_TRQ        = 2,
> +    RISCV_IOMMU_HPMEVENT_ATS_RQ     = 3,
> +    RISCV_IOMMU_HPMEVENT_TLB_MISS   = 4,
> +    RISCV_IOMMU_HPMEVENT_DD_WALK    = 5,
> +    RISCV_IOMMU_HPMEVENT_PD_WALK    = 6,
> +    RISCV_IOMMU_HPMEVENT_S_VS_WALKS = 7,
> +    RISCV_IOMMU_HPMEVENT_G_WALKS    = 8,
> +    RISCV_IOMMU_HPMEVENT_MAX        = 9
> +};
> +
>  /* 5.24 Translation request IOVA (64bits) */
>  #define RISCV_IOMMU_REG_TR_REQ_IOVA     0x0258
>
> --
> 2.47.1
>
>