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From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode
Date: Fri, 23 Oct 2020 16:29:52 -0700	[thread overview]
Message-ID: <CAKmqyKNRRa2-0tOv0GMqRAkRTmRED40tDpnOQ7LHhF_vVpgzAw@mail.gmail.com> (raw)
In-Reply-To: <bec11f34-9cfe-4aa2-2f9c-3781d7f5e8ad@linaro.org>

On Fri, Oct 23, 2020 at 12:13 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/23/20 8:26 AM, Alistair Francis wrote:
> > +++ b/target/riscv/cpu-param.h
> > @@ -18,6 +18,6 @@
> >  # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
> >  #endif
> >  #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
> > -#define NB_MMU_MODES 4
> > +#define NB_MMU_MODES 8
>
> Is there really a PRV_M + virt enabled state?

No, there isn't.

>
> > +#define TB_FLAGS_PRIV_MMU_MASK                3
> ...
> > -    int mode = mmu_idx;
> > +    int mode = mmu_idx & 0x3;
>
> Use that MASK here?

Good idea.

Alistair

>
>
> r~


  reply	other threads:[~2020-10-23 23:42 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-23 15:25 [PATCH v1 0/5] Fix the Hypervisor access functions Alistair Francis
2020-10-23 15:26 ` [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-10-23 19:13   ` Richard Henderson
2020-10-23 23:29     ` Alistair Francis [this message]
2020-10-23 15:26 ` [PATCH v1 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-10-23 15:26 ` [PATCH v1 3/5] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-10-23 15:26 ` [PATCH v1 4/5] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-10-23 15:26 ` [PATCH v1 5/5] target/riscv: Split the Hypervisor execute load helpers Alistair Francis

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