From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Anup Patel <anup@brainfault.org>,
Bin Meng <bin.meng@windriver.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Alistair Francis <alistair.francis@opensource.wdc.com>,
Bin Meng <bmeng.cn@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
Date: Mon, 20 Dec 2021 15:41:38 +1000 [thread overview]
Message-ID: <CAKmqyKNSUQGAUL16Qks9c-aY61K5wAFYqU+a8MV8Y=m_+T-Daw@mail.gmail.com> (raw)
In-Reply-To: <90fb8940-f684-f546-fd18-288af467df8d@amsat.org>
On Thu, Dec 16, 2021 at 6:18 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 12/16/21 06:58, Anup Patel wrote:
> > On Thu, Dec 16, 2021 at 10:27 AM Alistair Francis
> > <alistair.francis@opensource.wdc.com> wrote:
> >>
> >> From: Alistair Francis <alistair.francis@wdc.com>
> >>
> >> Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
> >> let's set that as the maximum for the virt board.
> >>
> >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
> >> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>
> > IMO, we should keep QEMU VIRT_CPUS_MAX as high as
> > possible to allow any kind of software Linux, OpenSBI, FreeBSD,
> > Xvisor, Xen, etc. Let the guest software decide it's own limit (such
> > as NR_CPUS of Linux).
>
> Agreed.
I agree as well. I'm happy to increase this in the future, the problem
is that I am only able to test it with 32 cores on Linux.
Alistair
next prev parent reply other threads:[~2021-12-20 6:53 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 4:54 [PATCH v2 0/9] A collection of RISC-V cleanups and improvements Alistair Francis
2021-12-16 4:54 ` [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function Alistair Francis
2021-12-16 8:16 ` Philippe Mathieu-Daudé
2021-12-21 8:00 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function Alistair Francis
2021-12-16 4:54 ` [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions Alistair Francis
2021-12-21 8:22 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental Alistair Francis
2021-12-16 5:59 ` Anup Patel
2021-12-20 2:52 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 2:53 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation Alistair Francis
2021-12-20 7:38 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores Alistair Francis
2021-12-16 5:58 ` Anup Patel
2021-12-16 8:18 ` Philippe Mathieu-Daudé
2021-12-20 5:41 ` Alistair Francis [this message]
2021-12-20 7:39 ` Bin Meng
2021-12-16 4:54 ` [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency Alistair Francis
2021-12-16 5:52 ` Anup Patel
2021-12-20 7:51 ` Bin Meng
2021-12-21 6:32 ` Alistair Francis
2021-12-21 6:56 ` Bin Meng
2022-02-22 15:41 ` Peter Maydell
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