* [PATCH 0/1 v3] [RISC-V/RVV] optimize the memory probing for vector fault-only-first loads.
@ 2025-03-12 19:22 Paolo Savini
2025-03-12 19:22 ` [PATCH 1/1 v3] target/riscv: " Paolo Savini
2025-03-19 1:39 ` [PATCH 0/1 v3] [RISC-V/RVV] " Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Paolo Savini @ 2025-03-12 19:22 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Paolo Savini, Richard Handerson, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Helene Chelin, Nathan Egge, Max Chou, Jeremy Bennett,
Craig Blackmore
Adding reviewer information to the patch and rebasing on top of master.
Previous versions:
- v1: https://lore.kernel.org/all/20250129144435.82451-1-paolo.savini@embecosm.com/
- v2: https://lore.kernel.org/all/20250221155320.59159-1-paolo.savini@embecosm.com/
Cc: Richard Handerson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>
Cc: Jeremy Bennett <jeremy.bennett@embecosm.com>
Cc: Craig Blackmore <craig.blackmore@embecosm.com>
Paolo Savini (1):
target/riscv: optimize the memory probing for vector fault-only-first
loads.
target/riscv/vector_helper.c | 103 ++++++++++++++++++++---------------
1 file changed, 58 insertions(+), 45 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/1 v3] target/riscv: optimize the memory probing for vector fault-only-first loads.
2025-03-12 19:22 [PATCH 0/1 v3] [RISC-V/RVV] optimize the memory probing for vector fault-only-first loads Paolo Savini
@ 2025-03-12 19:22 ` Paolo Savini
2025-03-19 1:39 ` [PATCH 0/1 v3] [RISC-V/RVV] " Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Paolo Savini @ 2025-03-12 19:22 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Paolo Savini, Richard Handerson, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Helene Chelin, Nathan Egge, Max Chou, Jeremy Bennett,
Craig Blackmore
Fault-only-first loads in the RISC-V vector extension need to update
the vl with the element index that causes an exception.
In order to ensure this the emulation of this instruction used to probe the
memory covered by the load operation with a loop that iterated over each element
so that when a flag was raised it was possible to set the vl to the
corresponding element index.
This loop was executed every time whether an exception happened or not.
This commit removes the per element memory probing from the main execution path
and adds a broad memory probing first. If this probing raises any flag that is
not a watchpoint flag (that per standard is allowed by this instruction) we
proceed with the per element probing to find the index of the element causing
the exception and set vl to such index.
Signed-off-by: Paolo Savini <paolo.savini@embecosm.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/vector_helper.c | 103 ++++++++++++++++++++---------------
1 file changed, 58 insertions(+), 45 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7773df6a7c..71b823d5d4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -633,47 +633,69 @@ vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env,
uint32_t esz = 1 << log2_esz;
uint32_t msize = nf * esz;
uint32_t vma = vext_vma(desc);
- target_ulong addr, offset, remain, page_split, elems;
+ target_ulong addr, addr_probe, addr_i, offset, remain, page_split, elems;
int mmu_index = riscv_env_mmu_index(env, false);
+ int flags;
+ void *host;
VSTART_CHECK_EARLY_EXIT(env);
- /* probe every access */
- for (i = env->vstart; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, i)) {
- continue;
- }
- addr = adjust_addr(env, base + i * (nf << log2_esz));
- if (i == 0) {
- /* Allow fault on first element. */
- probe_pages(env, addr, nf << log2_esz, ra, MMU_DATA_LOAD);
- } else {
- remain = nf << log2_esz;
- while (remain > 0) {
- void *host;
- int flags;
-
- offset = -(addr | TARGET_PAGE_MASK);
-
- /* Probe nonfault on subsequent elements. */
- flags = probe_access_flags(env, addr, offset, MMU_DATA_LOAD,
- mmu_index, true, &host, 0);
-
- /*
- * Stop if invalid (unmapped) or mmio (transaction may fail).
- * Do not stop if watchpoint, as the spec says that
- * first-fault should continue to access the same
- * elements regardless of any watchpoint.
- */
- if (flags & ~TLB_WATCHPOINT) {
- vl = i;
- goto ProbeSuccess;
- }
- if (remain <= offset) {
- break;
+ addr = base + ((env->vstart * nf) << log2_esz);
+ page_split = -(addr | TARGET_PAGE_MASK);
+ /* Get number of elements */
+ elems = page_split / msize;
+ if (unlikely(env->vstart + elems >= env->vl)) {
+ elems = env->vl - env->vstart;
+ }
+
+ /* Check page permission/pmp/watchpoint/etc. */
+ flags = probe_access_flags(env, adjust_addr(env, addr), elems * msize,
+ MMU_DATA_LOAD, mmu_index, true, &host, ra);
+
+ /* If we are crossing a page check also the second page. */
+ if (env->vl > elems) {
+ addr_probe = addr + (elems << log2_esz);
+ flags |= probe_access_flags(env, adjust_addr(env, addr_probe),
+ elems * msize, MMU_DATA_LOAD, mmu_index,
+ true, &host, ra);
+ }
+
+ if (flags & ~TLB_WATCHPOINT) {
+ /* probe every access */
+ for (i = env->vstart; i < env->vl; i++) {
+ if (!vm && !vext_elem_mask(v0, i)) {
+ continue;
+ }
+ addr_i = adjust_addr(env, base + i * (nf << log2_esz));
+ if (i == 0) {
+ /* Allow fault on first element. */
+ probe_pages(env, addr_i, nf << log2_esz, ra, MMU_DATA_LOAD);
+ } else {
+ remain = nf << log2_esz;
+ while (remain > 0) {
+ offset = -(addr_i | TARGET_PAGE_MASK);
+
+ /* Probe nonfault on subsequent elements. */
+ flags = probe_access_flags(env, addr_i, offset,
+ MMU_DATA_LOAD, mmu_index, true,
+ &host, 0);
+
+ /*
+ * Stop if invalid (unmapped) or mmio (transaction may
+ * fail). Do not stop if watchpoint, as the spec says that
+ * first-fault should continue to access the same
+ * elements regardless of any watchpoint.
+ */
+ if (flags & ~TLB_WATCHPOINT) {
+ vl = i;
+ goto ProbeSuccess;
+ }
+ if (remain <= offset) {
+ break;
+ }
+ remain -= offset;
+ addr_i = adjust_addr(env, addr_i + offset);
}
- remain -= offset;
- addr = adjust_addr(env, addr + offset);
}
}
}
@@ -685,15 +707,6 @@ ProbeSuccess:
if (env->vstart < env->vl) {
if (vm) {
- /* Calculate the page range of first page */
- addr = base + ((env->vstart * nf) << log2_esz);
- page_split = -(addr | TARGET_PAGE_MASK);
- /* Get number of elements */
- elems = page_split / msize;
- if (unlikely(env->vstart + elems >= env->vl)) {
- elems = env->vl - env->vstart;
- }
-
/* Load/store elements in the first page */
if (likely(elems)) {
vext_page_ldst_us(env, vd, addr, elems, nf, max_elems,
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 0/1 v3] [RISC-V/RVV] optimize the memory probing for vector fault-only-first loads.
2025-03-12 19:22 [PATCH 0/1 v3] [RISC-V/RVV] optimize the memory probing for vector fault-only-first loads Paolo Savini
2025-03-12 19:22 ` [PATCH 1/1 v3] target/riscv: " Paolo Savini
@ 2025-03-19 1:39 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2025-03-19 1:39 UTC (permalink / raw)
To: Paolo Savini
Cc: qemu-devel, qemu-riscv, Richard Handerson, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, Helene Chelin, Nathan Egge, Max Chou, Jeremy Bennett,
Craig Blackmore
On Thu, Mar 13, 2025 at 5:23 AM Paolo Savini <paolo.savini@embecosm.com> wrote:
>
> Adding reviewer information to the patch and rebasing on top of master.
>
> Previous versions:
>
> - v1: https://lore.kernel.org/all/20250129144435.82451-1-paolo.savini@embecosm.com/
> - v2: https://lore.kernel.org/all/20250221155320.59159-1-paolo.savini@embecosm.com/
This is already in the RISC-V tree, you don't need to resend it
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
Alistair
>
> Cc: Richard Handerson <richard.henderson@linaro.org>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Weiwei Li <liwei1518@gmail.com>
> Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
> Cc: Helene Chelin <helene.chelin@embecosm.com>
> Cc: Nathan Egge <negge@google.com>
> Cc: Max Chou <max.chou@sifive.com>
> Cc: Jeremy Bennett <jeremy.bennett@embecosm.com>
> Cc: Craig Blackmore <craig.blackmore@embecosm.com>
>
> Paolo Savini (1):
> target/riscv: optimize the memory probing for vector fault-only-first
> loads.
>
> target/riscv/vector_helper.c | 103 ++++++++++++++++++++---------------
> 1 file changed, 58 insertions(+), 45 deletions(-)
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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