From: Alistair Francis <alistair23@gmail.com>
To: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"cfu@mips.com" <cfu@mips.com>, "mst@redhat.com" <mst@redhat.com>,
"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
"philmd@linaro.org" <philmd@linaro.org>,
"thuth@redhat.com" <thuth@redhat.com>
Subject: Re: [PATCH v1 0/1] riscv: Update MIPS vendor id
Date: Wed, 5 Nov 2025 09:08:15 +1000 [thread overview]
Message-ID: <CAKmqyKNV9Dc5-mszwg8aFCkqLiASLZ_u+dbLLyG_59usMAL6Mw@mail.gmail.com> (raw)
In-Reply-To: <20251104150708.3345289-1-djordje.todorovic@htecgroup.com>
On Wed, Nov 5, 2025 at 1:07 AM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> We have already sent patch set for introducing MIPS's
> p8700 CPU in qemu at:
>
> https://patchew.org/QEMU/20251018154522.745788-1-djordje.todorovic@htecgroup.com/
That series was dropped as it failed to pass the CI tests:
https://patchew.org/QEMU/20251023041435.1775208-1-alistair.francis@wdc.com/
You can just include this change in a new patchset
Alistair
>
> So, this is a bugfix that should go on top of it.
>
> Djordje Todorovic (1):
> riscv: Update MIPS vendor id
>
> target/riscv/cpu_vendorid.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> --
> 2.34.1
next prev parent reply other threads:[~2025-11-04 23:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 15:07 [PATCH v1 0/1] riscv: Update MIPS vendor id Djordje Todorovic
2025-11-04 15:07 ` [PATCH v1 1/1] " Djordje Todorovic
2025-11-04 15:12 ` Daniel Henrique Barboza
2025-11-04 23:08 ` Alistair Francis [this message]
2025-11-06 10:16 ` [PATCH v1 0/1] " Djordje Todorovic
2025-11-06 10:46 ` Thomas Huth
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