From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Anup Patel <anup.patel@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Ivan Griffin <ivan.griffin@emdalo.com>
Subject: Re: [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory
Date: Tue, 27 Oct 2020 10:30:35 -0700 [thread overview]
Message-ID: <CAKmqyKNVUgV6Go6RdogLxhE5hOBr7aboe1indWTEaodep4MJLg@mail.gmail.com> (raw)
In-Reply-To: <20201027141740.18336-8-bmeng.cn@gmail.com>
On Tue, Oct 27, 2020 at 7:53 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Somehow HSS needs to access address 0 [1] for the DDR calibration data
> which is in the chipset's debug memory. Let's map the debug memory.
>
> [1] See the config_copy() calls in various places in ddr_setup() in
> the HSS source codes.
Really? This is reserved memory that they just read and write to? That's crazy.
If we really need this can you add a comment saying that the
documentation is wrong (again) and that this needs to be here.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/microchip_pfsoc.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 69117c6000..b9c2f73e7c 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -158,6 +158,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
> const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
> MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *debug_mem = g_new(MemoryRegion, 1);
> MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *envm_data = g_new(MemoryRegion, 1);
> @@ -177,6 +178,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
> qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
>
> + /* Debug */
This doesn't seem right.
Debug should start at 0x0000_0100 (it seems like what is currently in
tree is wrong).
Address 0x00 is marked as reserved in the documentation.
Do you mind updating the memory map to fix the debug address? Then
just add a reserved region as well.
Alistair
> + memory_region_init_ram(debug_mem, NULL, "microchip.pfsoc.debug_mem",
> + memmap[MICROCHIP_PFSOC_DEBUG].size, &error_fatal);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_DEBUG].base,
> + debug_mem);
> +
> /* E51 DTIM */
> memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
> memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2020-10-27 17:58 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Bin Meng
2020-10-27 20:45 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Bin Meng
2020-10-27 17:37 ` Alistair Francis
2020-10-28 1:43 ` Bin Meng
2020-10-28 14:13 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support Bin Meng
2020-10-27 20:48 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module Bin Meng
2020-10-27 17:42 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support Bin Meng
2020-10-27 20:51 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module Bin Meng
2020-10-27 17:42 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory Bin Meng
2020-10-27 17:30 ` Alistair Francis [this message]
2020-10-28 2:08 ` Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map Bin Meng
2020-10-27 20:55 ` Alistair Francis
2020-10-28 2:06 ` Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Bin Meng
2020-10-27 17:19 ` Alistair Francis
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