From: Alistair Francis <alistair23@gmail.com>
To: Max Chou <max.chou@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu.zevorn@gmail.com>
Subject: Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags
Date: Fri, 13 Mar 2026 10:59:38 +1000 [thread overview]
Message-ID: <CAKmqyKNVZmweVava8LyzEy+tu+UFDDgj+VX6Y-waYQEp8YbGbQ@mail.gmail.com> (raw)
In-Reply-To: <abKlW3gA3qXR6bub@sifive.com>
On Thu, Mar 12, 2026 at 9:42 PM Max Chou <max.chou@sifive.com> wrote:
>
> On 2026-03-09 15:01, Alistair Francis wrote:
> > On Fri, Mar 6, 2026 at 5:13 PM Max Chou <max.chou@sifive.com> wrote:
> > >
> > > We have more than 32-bits worth of state per TB, so use the
> > > tb->cs_base, which is otherwise unused for RISC-V, as the extend flag.
> > >
> > > Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> > > Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
> > > Signed-off-by: Max Chou <max.chou@sifive.com>
> > > ---
> > > include/exec/translation-block.h | 1 +
> > > target/riscv/cpu.h | 3 +++
> > > target/riscv/tcg/tcg-cpu.c | 7 ++++++-
> > > 3 files changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h
> > > index 4f83d5bec9..40cc699031 100644
> > > --- a/include/exec/translation-block.h
> > > +++ b/include/exec/translation-block.h
> > > @@ -65,6 +65,7 @@ struct TranslationBlock {
> > > * arm: an extension of tb->flags,
> > > * s390x: instruction data for EXECUTE,
> > > * sparc: the next pc of the instruction queue (for delay slots).
> > > + * riscv: an extension of tb->flags,
> > > */
> > > uint64_t cs_base;
> > >
> >
>
> Hi Alistair,
>
> I’m curious to know if you mean adding more details here, such as
> specifying the bit width for misa (e.g., 32 bits) or the bit width for
> ALTFMT (e.g., 1 bit).
> If so, I’ll include these details in the v6 version.
Oh! You did update the comment. Sorry I missed that.
No action required!
Alistair
>
> Thanks,
> rnax
>
> > We need to update the comment in `struct TranslationBlock` for
> > `target_ulong cs_base`
> >
> > Alistair
> >
next prev parent reply other threads:[~2026-03-13 1:00 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-06 7:10 [PATCH v5 0/9] Add Zvfbfa extension support Max Chou
2026-03-06 7:10 ` [PATCH v5 1/9] target/riscv: Add cfg properties for Zvfbfa extensions Max Chou
2026-03-09 4:44 ` Alistair Francis
2026-03-06 7:10 ` [PATCH v5 2/9] target/riscv: Add the Zvfbfa extension implied rule Max Chou
2026-03-09 4:45 ` Alistair Francis
2026-03-06 7:10 ` [PATCH v5 3/9] target/riscv: rvv: Add new VTYPE CSR field - altfmt Max Chou
2026-03-09 4:55 ` Alistair Francis
2026-03-16 9:20 ` Nutty.Liu
2026-03-06 7:10 ` [PATCH v5 4/9] target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype CSR Max Chou
2026-03-09 4:55 ` Alistair Francis
2026-03-16 9:22 ` Nutty.Liu
2026-03-06 7:11 ` [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags Max Chou
2026-03-09 5:01 ` Alistair Francis
2026-03-12 11:42 ` Max Chou
2026-03-13 0:59 ` Alistair Francis [this message]
2026-03-06 7:11 ` [PATCH v5 6/9] target/riscv: Introduce altfmt into DisasContext Max Chou
2026-03-09 5:02 ` Alistair Francis
2026-03-06 7:11 ` [PATCH v5 7/9] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension Max Chou
2026-03-09 5:04 ` Alistair Francis
2026-03-06 7:11 ` [PATCH v5 8/9] target/riscv: rvv: Support Zvfbfa vector bf16 operations Max Chou
2026-03-06 7:11 ` [PATCH v5 9/9] target/riscv: Expose Zvfbfa extension as an experimental cpu property Max Chou
2026-03-09 4:51 ` [PATCH v5 0/9] Add Zvfbfa extension support Alistair Francis
2026-03-12 11:16 ` Max Chou
2026-03-13 1:09 ` Alistair Francis
2026-03-16 8:28 ` Max Chou
2026-03-19 3:45 ` Alistair Francis
2026-03-26 3:42 ` Max Chou
2026-03-26 6:07 ` Chao Liu
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