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Thu, 12 Mar 2026 18:00:04 -0700 (PDT) MIME-Version: 1.0 References: <20260306071105.3328365-1-max.chou@sifive.com> <20260306071105.3328365-6-max.chou@sifive.com> In-Reply-To: From: Alistair Francis Date: Fri, 13 Mar 2026 10:59:38 +1000 X-Gm-Features: AaiRm53k81TF3oabmpcFRgs75qTCoudd7HXGEGgS3bbEyDyLVyY9LaSlzMzTNnQ Message-ID: Subject: Re: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags To: Max Chou Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Mar 12, 2026 at 9:42=E2=80=AFPM Max Chou wrot= e: > > On 2026-03-09 15:01, Alistair Francis wrote: > > On Fri, Mar 6, 2026 at 5:13=E2=80=AFPM Max Chou w= rote: > > > > > > We have more than 32-bits worth of state per TB, so use the > > > tb->cs_base, which is otherwise unused for RISC-V, as the extend flag= . > > > > > > Reviewed-by: Daniel Henrique Barboza > > > Reviewed-by: Chao Liu > > > Signed-off-by: Max Chou > > > --- > > > include/exec/translation-block.h | 1 + > > > target/riscv/cpu.h | 3 +++ > > > target/riscv/tcg/tcg-cpu.c | 7 ++++++- > > > 3 files changed, 10 insertions(+), 1 deletion(-) > > > > > > diff --git a/include/exec/translation-block.h b/include/exec/translat= ion-block.h > > > index 4f83d5bec9..40cc699031 100644 > > > --- a/include/exec/translation-block.h > > > +++ b/include/exec/translation-block.h > > > @@ -65,6 +65,7 @@ struct TranslationBlock { > > > * arm: an extension of tb->flags, > > > * s390x: instruction data for EXECUTE, > > > * sparc: the next pc of the instruction queue (for delay slots)= . > > > + * riscv: an extension of tb->flags, > > > */ > > > uint64_t cs_base; > > > > > > > Hi Alistair, > > I=E2=80=99m curious to know if you mean adding more details here, such as > specifying the bit width for misa (e.g., 32 bits) or the bit width for > ALTFMT (e.g., 1 bit). > If so, I=E2=80=99ll include these details in the v6 version. Oh! You did update the comment. Sorry I missed that. No action required! Alistair > > Thanks, > rnax > > > We need to update the comment in `struct TranslationBlock` for > > `target_ulong cs_base` > > > > Alistair > >