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Iglesias" , Alistair Francis , Peter Maydell , Jason Wang , Palmer Dabbelt , qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=alistair23@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Oct 5, 2025 at 6:03=E2=80=AFAM Guenter Roeck w= rote: > > The Linux kernel checks the PCS disabled bit in the R_DESCONF register > to determine if SGMII is supported. If the bit is set, SGMII support is > disabled. Since the Microchip Icicle devicetree file configures SGMII > interface mode, enabling the Ethernet interfaces fails when booting > the Linux kernel. > > Add pcs-enabled property to to let the driver know if PCS should be > enabled. Set the flag to false by default (indicating that PCS is disable= d) > to match the exiting code. > > Signed-off-by: Guenter Roeck Acked-by: Alistair Francis Alistair > --- > hw/net/cadence_gem.c | 7 ++++++- > include/hw/net/cadence_gem.h | 1 + > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c > index 520324adfd..44896f1801 100644 > --- a/hw/net/cadence_gem.c > +++ b/hw/net/cadence_gem.c > @@ -1477,7 +1477,10 @@ static void gem_reset(DeviceState *d) > s->regs[R_TXPARTIALSF] =3D 0x000003ff; > s->regs[R_RXPARTIALSF] =3D 0x000003ff; > s->regs[R_MODID] =3D s->revision; > - s->regs[R_DESCONF] =3D 0x02D00111; > + s->regs[R_DESCONF] =3D 0x02D00110; > + if (!s->pcs_enabled) { > + s->regs[R_DESCONF] |=3D 0x00000001; > + } > s->regs[R_DESCONF2] =3D 0x2ab10000 | s->jumbo_max_len; > s->regs[R_DESCONF5] =3D 0x002f2045; > s->regs[R_DESCONF6] =3D R_DESCONF6_DMA_ADDR_64B_MASK; > @@ -1821,6 +1824,8 @@ static const Property gem_properties[] =3D { > num_type2_screeners, 4), > DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, > jumbo_max_len, 10240), > + DEFINE_PROP_BOOL("pcs-enabled", CadenceGEMState, > + pcs_enabled, false), > DEFINE_PROP_BOOL("phy-connected", CadenceGEMState, phy_connected, tr= ue), > DEFINE_PROP_LINK("phy-consumer", CadenceGEMState, phy_consumer, > TYPE_CADENCE_GEM, CadenceGEMState *), > diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h > index 21e7319f53..e63941f18f 100644 > --- a/include/hw/net/cadence_gem.h > +++ b/include/hw/net/cadence_gem.h > @@ -62,6 +62,7 @@ struct CadenceGEMState { > uint8_t num_type2_screeners; > uint32_t revision; > uint16_t jumbo_max_len; > + bool pcs_enabled; > > /* GEM registers backing store */ > uint32_t regs[CADENCE_GEM_MAXREG]; > -- > 2.45.2 > >