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From: Alistair Francis <alistair23@gmail.com>
To: Weiwei Li <liweiwei@iscas.ac.cn>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
	 alistair.francis@wdc.com, bin.meng@windriver.com,
	dbarboza@ventanamicro.com,  zhiwei_liu@linux.alibaba.com,
	wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
Date: Fri, 26 May 2023 11:22:29 +1000	[thread overview]
Message-ID: <CAKmqyKNXL8DvHJSuXZZDjCfDpKGVoJ-HisZ4NpwiFNkq2L_eEA@mail.gmail.com> (raw)
In-Reply-To: <20230523093539.203909-4-liweiwei@iscas.ac.cn>

On Tue, May 23, 2023 at 7:38 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Pass RISCVCPUConfig as disassemble_info.target_info to support disas
> of conflict instructions related to specific extensions.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  disas/riscv.c      | 10 +++++++---
>  target/riscv/cpu.c |  1 +
>  2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index e61bda5674..729ab684da 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -19,7 +19,7 @@
>
>  #include "qemu/osdep.h"
>  #include "disas/dis-asm.h"
> -
> +#include "target/riscv/cpu_cfg.h"
>
>  /* types */
>
> @@ -967,6 +967,7 @@ typedef enum {
>  /* structures */
>
>  typedef struct {
> +    RISCVCPUConfig *cfg;
>      uint64_t  pc;
>      uint64_t  inst;
>      int32_t   imm;
> @@ -4855,11 +4856,13 @@ static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
>  /* disassemble instruction */
>
>  static void
> -disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
> +disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst,
> +            RISCVCPUConfig *cfg)
>  {
>      rv_decode dec = { 0 };
>      dec.pc = pc;
>      dec.inst = inst;
> +    dec.cfg = cfg;
>      decode_inst_opcode(&dec, isa);
>      decode_inst_operands(&dec, isa);
>      decode_inst_decompress(&dec, isa);
> @@ -4914,7 +4917,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
>          break;
>      }
>
> -    disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
> +    disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
> +                (RISCVCPUConfig *)info->target_info);
>      (*info->fprintf_func)(info->stream, "%s", buf);
>
>      return len;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db0875fb43..4fe926cdd1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -818,6 +818,7 @@ static void riscv_cpu_reset_hold(Object *obj)
>  static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
>  {
>      RISCVCPU *cpu = RISCV_CPU(s);
> +    info->target_info = &cpu->cfg;
>
>      switch (riscv_cpu_mxl(&cpu->env)) {
>      case MXL_RV32:
> --
> 2.25.1
>
>


  reply	other threads:[~2023-05-26  1:23 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-23  9:35 [PATCH v2 0/8] Add support for extension specific disas Weiwei Li
2023-05-23  9:35 ` [PATCH v2 1/8] disas: Change type of disassemble_info.target_info to pointer Weiwei Li
2023-05-26  1:20   ` Alistair Francis
2023-05-23  9:35 ` [PATCH v2 2/8] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Weiwei Li
2023-05-23 12:15   ` Daniel Henrique Barboza
2023-05-26  1:19   ` Alistair Francis
2023-05-23  9:35 ` [PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Weiwei Li
2023-05-26  1:22   ` Alistair Francis [this message]
2023-05-23  9:35 ` [PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions Weiwei Li
2023-05-26  1:23   ` Alistair Francis
2023-05-23  9:35 ` [PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions Weiwei Li
2023-05-26  1:24   ` Alistair Francis
2023-05-23  9:35 ` [PATCH v2 6/8] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Weiwei Li
2023-05-26  1:25   ` Alistair Francis
2023-05-23  9:35 ` [PATCH v2 7/8] disas/riscv.c: Fix lines with over 80 characters Weiwei Li
2023-05-26  1:25   ` Alistair Francis
2023-05-23  9:35 ` [PATCH v2 8/8] disas/riscv.c: Remove redundant parentheses Weiwei Li
2023-05-26  1:26   ` Alistair Francis
2023-05-26  1:35 ` [PATCH v2 0/8] Add support for extension specific disas Alistair Francis

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