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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2a; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, May 23, 2023 at 7:38=E2=80=AFPM Weiwei Li wr= ote: > > Pass RISCVCPUConfig as disassemble_info.target_info to support disas > of conflict instructions related to specific extensions. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > disas/riscv.c | 10 +++++++--- > target/riscv/cpu.c | 1 + > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/disas/riscv.c b/disas/riscv.c > index e61bda5674..729ab684da 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -19,7 +19,7 @@ > > #include "qemu/osdep.h" > #include "disas/dis-asm.h" > - > +#include "target/riscv/cpu_cfg.h" > > /* types */ > > @@ -967,6 +967,7 @@ typedef enum { > /* structures */ > > typedef struct { > + RISCVCPUConfig *cfg; > uint64_t pc; > uint64_t inst; > int32_t imm; > @@ -4855,11 +4856,13 @@ static void decode_inst_decompress(rv_decode *dec= , rv_isa isa) > /* disassemble instruction */ > > static void > -disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst i= nst) > +disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst i= nst, > + RISCVCPUConfig *cfg) > { > rv_decode dec =3D { 0 }; > dec.pc =3D pc; > dec.inst =3D inst; > + dec.cfg =3D cfg; > decode_inst_opcode(&dec, isa); > decode_inst_operands(&dec, isa); > decode_inst_decompress(&dec, isa); > @@ -4914,7 +4917,8 @@ print_insn_riscv(bfd_vma memaddr, struct disassembl= e_info *info, rv_isa isa) > break; > } > > - disasm_inst(buf, sizeof(buf), isa, memaddr, inst); > + disasm_inst(buf, sizeof(buf), isa, memaddr, inst, > + (RISCVCPUConfig *)info->target_info); > (*info->fprintf_func)(info->stream, "%s", buf); > > return len; > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index db0875fb43..4fe926cdd1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -818,6 +818,7 @@ static void riscv_cpu_reset_hold(Object *obj) > static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info= ) > { > RISCVCPU *cpu =3D RISCV_CPU(s); > + info->target_info =3D &cpu->cfg; > > switch (riscv_cpu_mxl(&cpu->env)) { > case MXL_RV32: > -- > 2.25.1 > >