From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com, ajones@ventanamicro.com,
vladimir.isaev@syntacore.com
Subject: Re: [PATCH v3 05/16] target/riscv: move 'pmp' to riscv_cpu_properties[]
Date: Fri, 5 Jan 2024 15:03:00 +1000 [thread overview]
Message-ID: <CAKmqyKNXX9a3M4f=+mCoq_i_-rLi-pAB_uj0FNC3XL-xwe3jXg@mail.gmail.com> (raw)
In-Reply-To: <20240103174013.147279-6-dbarboza@ventanamicro.com>
On Thu, Jan 4, 2024 at 4:53 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Move 'pmp' to riscv_cpu_properties[], creating a new setter() for it
> that forbids 'pmp' to be changed in vendor CPUs, like we did with the
> 'mmu' option.
>
> We'll also have to manually set 'pmp = true' to generic CPUs that were
> still relying on the previous default to set it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 38 ++++++++++++++++++++++++++++++++++++--
> 1 file changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9f1407b73f..01b3b57cee 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -420,6 +420,7 @@ static void riscv_max_cpu_init(Object *obj)
> RISCVMXL mlx = MXL_RV64;
>
> cpu->cfg.mmu = true;
> + cpu->cfg.pmp = true;
>
> #ifdef TARGET_RISCV32
> mlx = MXL_RV32;
> @@ -439,6 +440,7 @@ static void rv64_base_cpu_init(Object *obj)
> CPURISCVState *env = &cpu->env;
>
> cpu->cfg.mmu = true;
> + cpu->cfg.pmp = true;
>
> /* We set this in the realise function */
> riscv_cpu_set_misa(env, MXL_RV64, 0);
> @@ -568,6 +570,7 @@ static void rv128_base_cpu_init(Object *obj)
> }
>
> cpu->cfg.mmu = true;
> + cpu->cfg.pmp = true;
>
> /* We set this in the realise function */
> riscv_cpu_set_misa(env, MXL_RV128, 0);
> @@ -584,6 +587,7 @@ static void rv32_base_cpu_init(Object *obj)
> CPURISCVState *env = &cpu->env;
>
> cpu->cfg.mmu = true;
> + cpu->cfg.pmp = true;
>
> /* We set this in the realise function */
> riscv_cpu_set_misa(env, MXL_RV32, 0);
> @@ -1596,9 +1600,38 @@ static const PropertyInfo prop_mmu = {
> .set = prop_mmu_set,
> };
>
> -Property riscv_cpu_options[] = {
> - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> +static void prop_pmp_set(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + RISCVCPU *cpu = RISCV_CPU(obj);
> + bool value;
> +
> + visit_type_bool(v, name, &value, errp);
>
> + if (cpu->cfg.pmp != value && riscv_cpu_is_vendor(obj)) {
> + cpu_set_prop_err(cpu, name, errp);
> + return;
> + }
> +
> + cpu_option_add_user_setting(name, value);
> + cpu->cfg.pmp = value;
> +}
> +
> +static void prop_pmp_get(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + bool value = RISCV_CPU(obj)->cfg.pmp;
> +
> + visit_type_bool(v, name, &value, errp);
> +}
> +
> +static const PropertyInfo prop_pmp = {
> + .name = "pmp",
> + .get = prop_pmp_get,
> + .set = prop_pmp_set,
> +};
> +
> +Property riscv_cpu_options[] = {
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
>
> @@ -1618,6 +1651,7 @@ static Property riscv_cpu_properties[] = {
> {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */
>
> {.name = "mmu", .info = &prop_mmu},
> + {.name = "pmp", .info = &prop_pmp},
>
> #ifndef CONFIG_USER_ONLY
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2024-01-05 5:05 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-03 17:39 [PATCH v3 00/16] target/riscv: deprecate riscv_cpu_options[] Daniel Henrique Barboza
2024-01-03 17:39 ` [PATCH v3 01/16] target/riscv/cpu_cfg.h: remove unused fields Daniel Henrique Barboza
2024-01-05 3:51 ` Alistair Francis
2024-01-03 17:39 ` [PATCH v3 02/16] target/riscv: make riscv_cpu_is_generic() public Daniel Henrique Barboza
2024-01-05 3:51 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 03/16] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] Daniel Henrique Barboza
2024-01-05 3:55 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 04/16] target/riscv: move 'mmu' " Daniel Henrique Barboza
2024-01-05 5:00 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 05/16] target/riscv: move 'pmp' " Daniel Henrique Barboza
2024-01-05 5:03 ` Alistair Francis [this message]
2024-01-03 17:40 ` [PATCH v3 06/16] target/riscv: rework 'priv_spec' Daniel Henrique Barboza
2024-01-05 4:23 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 07/16] target/riscv: rework 'vext_spec' Daniel Henrique Barboza
2024-01-05 5:15 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[] Daniel Henrique Barboza
2024-01-05 5:05 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 09/16] target/riscv: move 'elen' " Daniel Henrique Barboza
2024-01-05 5:17 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 10/16] target/riscv: create finalize_features() for KVM Daniel Henrique Barboza
2024-01-05 4:54 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 11/16] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[] Daniel Henrique Barboza
2024-01-05 4:56 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 12/16] target/riscv: move 'cboz_blocksize' " Daniel Henrique Barboza
2024-01-05 4:57 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 13/16] target/riscv: remove riscv_cpu_options[] Daniel Henrique Barboza
2024-01-05 5:01 ` Alistair Francis
2024-01-03 17:40 ` [PATCH v3 14/16] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[] Daniel Henrique Barboza
2024-01-03 17:40 ` [PATCH v3 15/16] target/riscv/cpu.c: move 'mimpid' " Daniel Henrique Barboza
2024-01-03 17:40 ` [PATCH v3 16/16] target/riscv/cpu.c: move 'marchid' " Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAKmqyKNXX9a3M4f=+mCoq_i_-rLi-pAB_uj0FNC3XL-xwe3jXg@mail.gmail.com' \
--to=alistair23@gmail.com \
--cc=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=vladimir.isaev@syntacore.com \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).