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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e30; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe30.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jan 4, 2024 at 4:53=E2=80=AFAM Daniel Henrique Barboza wrote: > > Move 'pmp' to riscv_cpu_properties[], creating a new setter() for it > that forbids 'pmp' to be changed in vendor CPUs, like we did with the > 'mmu' option. > > We'll also have to manually set 'pmp =3D true' to generic CPUs that were > still relying on the previous default to set it. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 38 ++++++++++++++++++++++++++++++++++++-- > 1 file changed, 36 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9f1407b73f..01b3b57cee 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -420,6 +420,7 @@ static void riscv_max_cpu_init(Object *obj) > RISCVMXL mlx =3D MXL_RV64; > > cpu->cfg.mmu =3D true; > + cpu->cfg.pmp =3D true; > > #ifdef TARGET_RISCV32 > mlx =3D MXL_RV32; > @@ -439,6 +440,7 @@ static void rv64_base_cpu_init(Object *obj) > CPURISCVState *env =3D &cpu->env; > > cpu->cfg.mmu =3D true; > + cpu->cfg.pmp =3D true; > > /* We set this in the realise function */ > riscv_cpu_set_misa(env, MXL_RV64, 0); > @@ -568,6 +570,7 @@ static void rv128_base_cpu_init(Object *obj) > } > > cpu->cfg.mmu =3D true; > + cpu->cfg.pmp =3D true; > > /* We set this in the realise function */ > riscv_cpu_set_misa(env, MXL_RV128, 0); > @@ -584,6 +587,7 @@ static void rv32_base_cpu_init(Object *obj) > CPURISCVState *env =3D &cpu->env; > > cpu->cfg.mmu =3D true; > + cpu->cfg.pmp =3D true; > > /* We set this in the realise function */ > riscv_cpu_set_misa(env, MXL_RV32, 0); > @@ -1596,9 +1600,38 @@ static const PropertyInfo prop_mmu =3D { > .set =3D prop_mmu_set, > }; > > -Property riscv_cpu_options[] =3D { > - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > +static void prop_pmp_set(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVCPU *cpu =3D RISCV_CPU(obj); > + bool value; > + > + visit_type_bool(v, name, &value, errp); > > + if (cpu->cfg.pmp !=3D value && riscv_cpu_is_vendor(obj)) { > + cpu_set_prop_err(cpu, name, errp); > + return; > + } > + > + cpu_option_add_user_setting(name, value); > + cpu->cfg.pmp =3D value; > +} > + > +static void prop_pmp_get(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + bool value =3D RISCV_CPU(obj)->cfg.pmp; > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static const PropertyInfo prop_pmp =3D { > + .name =3D "pmp", > + .get =3D prop_pmp_get, > + .set =3D prop_pmp_set, > +}; > + > +Property riscv_cpu_options[] =3D { > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > > @@ -1618,6 +1651,7 @@ static Property riscv_cpu_properties[] =3D { > {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ > > {.name =3D "mmu", .info =3D &prop_mmu}, > + {.name =3D "pmp", .info =3D &prop_pmp}, > > #ifndef CONFIG_USER_ONLY > DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVE= C), > -- > 2.43.0 > >