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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92b; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Sep 25, 2024 at 9:59=E2=80=AFPM Cl=C3=A9ment L=C3=A9ger wrote: > > When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode > while SSTATUS.SDT isn't cleared, generate a double trap exception to > M-mode. > > Signed-off-by: Cl=C3=A9ment L=C3=A9ger > --- > target/riscv/cpu.c | 2 +- > target/riscv/cpu_bits.h | 1 + > target/riscv/cpu_helper.c | 47 ++++++++++++++++++++++++++++++++++----- > 3 files changed, 43 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cf06cd741a..65347ccd5a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -284,7 +284,7 @@ static const char * const riscv_excp_names[] =3D { > "load_page_fault", > "reserved", > "store_page_fault", > - "reserved", > + "double_trap", > "reserved", > "reserved", > "reserved", > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 3a5588d4df..5557a86348 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -699,6 +699,7 @@ typedef enum RISCVException { > RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ > RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ > RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ > + RISCV_EXCP_DOUBLE_TRAP =3D 0x10, > RISCV_EXCP_SW_CHECK =3D 0x12, /* since: priv-1.13.0 */ > RISCV_EXCP_HW_ERR =3D 0x13, /* since: priv-1.13.0 */ > RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 395d8235ce..69da3c3384 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -575,7 +575,9 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *en= v) > mstatus_mask |=3D MSTATUS_FS; > } > bool current_virt =3D env->virt_enabled; > - > + if (riscv_env_smode_dbltrp_enabled(env, current_virt)) { > + mstatus_mask |=3D MSTATUS_SDT; > + } > g_assert(riscv_has_ext(env, RVH)); > > if (current_virt) { > @@ -1707,6 +1709,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > CPURISCVState *env =3D &cpu->env; > bool virt =3D env->virt_enabled; > bool write_gva =3D false; > + bool vsmode_exc; > uint64_t s; > int mode; > > @@ -1721,6 +1724,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) > !(env->mip & (1 << cause)); > bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && > !(env->mip & (1 << cause)); > + bool smode_double_trap =3D false; > + uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; > target_ulong tval =3D 0; > target_ulong tinst =3D 0; > target_ulong htval =3D 0; > @@ -1837,13 +1842,35 @@ void riscv_cpu_do_interrupt(CPUState *cs) > !async && > mode =3D=3D PRV_M; > > + vsmode_exc =3D env->virt_enabled && (((hdeleg >> cause) & 1) || vs_i= njected); > + /* > + * Check double trap condition only if already in S-mode and targeti= ng > + * S-mode > + */ > + if (cpu->cfg.ext_ssdbltrp && env->priv =3D=3D PRV_S && mode =3D=3D P= RV_S) { > + bool dte =3D (env->menvcfg & MENVCFG_DTE) !=3D 0; > + bool sdt =3D (env->mstatus & MSTATUS_SDT) !=3D 0; > + /* In VS or HS */ > + if (riscv_has_ext(env, RVH)) { > + if (vsmode_exc) { > + /* VS -> VS */ > + /* Stay in VS mode, use henvcfg instead of menvcfg*/ > + dte =3D (env->henvcfg & HENVCFG_DTE) !=3D 0; > + } else if (env->virt_enabled) { > + /* VS -> HS */ > + dte =3D false; I don't follow why this is false Alistair