From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
甲一 <lzw194868@alibaba-inc.com>
Subject: Re: [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU
Date: Fri, 12 Jul 2024 11:34:15 +1000 [thread overview]
Message-ID: <CAKmqyKN_+Hir5W1MPqpRhW_1b3M0kiRufX1M2__KcPrZY5guUg@mail.gmail.com> (raw)
In-Reply-To: <20240710022430.1306-1-zhiwei_liu@linux.alibaba.com>
On Wed, Jul 10, 2024 at 12:27 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> From: 甲一 <lzw194868@alibaba-inc.com>
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado test in tests/avocado.
>
> # make check-avocado AVOCADO_TESTS=/home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> VENVPIP install -e /home/jenkins/git/qemu/python/
> /home/jenkins/git/qemu/build/pyvenv/bin/python3 -B /home/jenkins/git/qemu/python/scripts/mkvenv.py ensuregroup --online /home/jenkins/git/qemu/pythondeps.toml avocado
> mkvenv: checking for avocado-framework(>=88.1, <93.0)
> mkvenv: checking for pycdlib>=1.11.0
> mkvenv: installing avocado-framework==88.1, pycdlib>=1.11.0
> AVOCADO tests/avocado
> Fetching asset from /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> Fetching asset from /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
> JOB ID : 8c2e1ff918d3111d078a52eba9956893afaf9e1d
> JOB LOG : /home/jenkins/git/qemu/build/tests/results/job-2024-07-10T09.55-8c2e1ff/job.log
> (1/1) /home/jenkins/git/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i: PASS (17.50 s)
> RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
> JOB TIME : 29.50 s
>
> v5:
> Rebase to master and add tags
>
> v4:
> Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
> Avocado: Add "if=none" to "-drive" option in QEMU command line
>
> v3:
> Rebase to the master branch
>
> v2:
> Remove the line that was inadvertently left in PATCH v1 4/6.
> Add an avocado test.
>
> v1:
> https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
>
> TANG Tiancheng (7):
> target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> target/riscv: Detect sxl to set bit width for RV32 in RV64
> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
> target/riscv: Enable RV32 CPU support in RV64 QEMU
> tests/avocado: Add an avocado test for riscv64
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> configs/targets/riscv64-softmmu.mak | 2 +-
> hw/riscv/boot.c | 35 +++++++++++++++++---------
> hw/riscv/sifive_u.c | 3 ++-
> include/hw/riscv/boot.h | 4 ++-
> include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++
> target/riscv/cpu.c | 17 ++++++++++---
> target/riscv/cpu.h | 5 +++-
> target/riscv/cpu_helper.c | 25 +++++++++++++------
> target/riscv/pmp.c | 2 +-
> tests/avocado/boot_linux_console.py | 38 +++++++++++++++++++++++++++++
> 10 files changed, 132 insertions(+), 28 deletions(-)
>
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2024-07-12 1:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-10 2:24 [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 6/7] target/riscv: Enable RV32 CPU support " LIU Zhiwei
2024-07-10 2:24 ` [PATCH v5 7/7] tests/avocado: Add an avocado test for riscv64 LIU Zhiwei
2024-07-12 9:52 ` Daniel Henrique Barboza
2024-07-15 1:29 ` LIU Zhiwei
2024-07-15 8:42 ` Daniel Henrique Barboza
2024-07-12 1:34 ` Alistair Francis [this message]
2024-07-12 9:57 ` [PATCH v5 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU Daniel Henrique Barboza
2024-07-15 1:31 ` LIU Zhiwei
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