From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, "Weiwei Li" <liwei1518@gmail.com>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Warner Losh" <imp@bsdimp.com>,
"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
"Vijai Kumar K" <vijai@behindbytes.com>,
"Anton Johansson" <anjo@rev.ng>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
qemu-riscv@nongnu.org,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Djordje Todorovic" <Djordje.Todorovic@htecgroup.com>
Subject: Re: [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model
Date: Thu, 26 Mar 2026 12:06:58 +1000 [thread overview]
Message-ID: <CAKmqyKN_BSB-n5CJnniFkB+YXdrY6BuRbsZee9ity3v_vD64GQ@mail.gmail.com> (raw)
In-Reply-To: <20260318103122.97244-5-philmd@linaro.org>
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
>
> We had to check that mttcg was not used when executing QEMU with
> -cpu x-rv128 as a single 128-bit access was done as two distinct
> 64-bit accesses.
> Now that we use the 128-bit ld/st that access the data atomically,
> this check is no longer necessary.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Message-ID: <20260101181442.2489496-3-frederic.petrot@univ-grenoble-alpes.fr>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 988b2d905f5..3407191c224 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
> }
>
> #ifndef CONFIG_USER_ONLY
> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> -
> - if (mcc->def->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
> - /* Missing 128-bit aligned atomics */
> - error_setg(errp,
> - "128-bit RISC-V currently does not work with Multi "
> - "Threaded TCG. Please use: -accel tcg,thread=single");
> - return false;
> - }
> -
> CPURISCVState *env = &cpu->env;
>
> tcg_cflags_set(CPU(cs), CF_PCREL);
> --
> 2.53.0
>
>
next prev parent reply other threads:[~2026-03-26 2:07 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-18 10:31 [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Philippe Mathieu-Daudé
2026-03-18 10:31 ` [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Philippe Mathieu-Daudé
2026-03-19 1:43 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 02/16] target/riscv: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
2026-03-19 3:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 03/16] target/riscv: Make LQ and SQ use 128-bit ld/st Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé
2026-03-26 2:06 ` Alistair Francis [this message]
2026-03-18 10:31 ` [PATCH-for-11.1 05/16] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) Philippe Mathieu-Daudé
2026-03-26 2:07 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release Philippe Mathieu-Daudé
2026-03-26 2:08 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub Philippe Mathieu-Daudé
2026-03-26 2:09 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 08/16] target/riscv: Simplify riscv_cpu_gdb_write_register() Philippe Mathieu-Daudé
2026-03-26 2:12 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 09/16] target/riscv: Expose mo_endian_env() Philippe Mathieu-Daudé
2026-03-26 2:13 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 10/16] target/riscv: Have gdbstub consider CPU endianness Philippe Mathieu-Daudé
2026-03-26 2:15 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 11/16] target/riscv: Replace MO_TE by mo_endian (MIPS extension) Philippe Mathieu-Daudé
2026-03-26 2:17 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 12/16] target/riscv: Replace MO_TE by mo_endian (Zilsd extension) Philippe Mathieu-Daudé
2026-03-26 2:18 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 13/16] target/riscv: Replace MO_TE by mo_endian (Zalasr extension) Philippe Mathieu-Daudé
2026-03-26 2:20 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 14/16] target/riscv: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-18 10:31 ` [PATCH-for-11.1 15/16] target/riscv: Use MO_LE for instruction fetch Philippe Mathieu-Daudé
2026-03-20 11:27 ` Djordje Todorovic
2026-03-18 10:31 ` [PATCH-for-11.1 16/16] configs/targets: Forbid RISC-V to use legacy native endianness APIs Philippe Mathieu-Daudé
2026-03-26 2:21 ` Alistair Francis
2026-03-26 2:28 ` [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API Alistair Francis
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