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Wed, 25 Mar 2026 19:07:25 -0700 (PDT) MIME-Version: 1.0 References: <20260318103122.97244-1-philmd@linaro.org> <20260318103122.97244-5-philmd@linaro.org> In-Reply-To: <20260318103122.97244-5-philmd@linaro.org> From: Alistair Francis Date: Thu, 26 Mar 2026 12:06:58 +1000 X-Gm-Features: AQROBzDqkRvqjsyg9ydAZWA1CPaFO1AgTbOKLM_NsVXS-sMwVkhcvv1n3FhiZuE Message-ID: Subject: Re: [PATCH-for-11.1 04/16] target/riscv: Remove MTTCG check for x-rv128 CPU model To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Weiwei Li , Pierrick Bouvier , Warner Losh , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , Vijai Kumar K , Anton Johansson , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Jiaxun Yang , Peter Maydell , Liu Zhiwei , Djordje Todorovic Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 18, 2026 at 8:33=E2=80=AFPM Philippe Mathieu-Daud=C3=A9 wrote: > > From: Fr=C3=A9d=C3=A9ric P=C3=A9trot > > We had to check that mttcg was not used when executing QEMU with > -cpu x-rv128 as a single 128-bit access was done as two distinct > 64-bit accesses. > Now that we use the 128-bit ld/st that access the data atomically, > this check is no longer necessary. > > Signed-off-by: Fr=C3=A9d=C3=A9ric P=C3=A9trot > Message-ID: <20260101181442.2489496-3-frederic.petrot@univ-grenoble-alpes= .fr> > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > target/riscv/tcg/tcg-cpu.c | 10 ---------- > 1 file changed, 10 deletions(-) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 988b2d905f5..3407191c224 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1305,16 +1305,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Er= ror **errp) > } > > #ifndef CONFIG_USER_ONLY > - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); > - > - if (mcc->def->misa_mxl_max >=3D MXL_RV128 && qemu_tcg_mttcg_enabled(= )) { > - /* Missing 128-bit aligned atomics */ > - error_setg(errp, > - "128-bit RISC-V currently does not work with Multi " > - "Threaded TCG. Please use: -accel tcg,thread=3Dsingle= "); > - return false; > - } > - > CPURISCVState *env =3D &cpu->env; > > tcg_cflags_set(CPU(cs), CF_PCREL); > -- > 2.53.0 > >