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Tue, 24 Mar 2026 19:21:12 -0700 (PDT) MIME-Version: 1.0 References: <20260321144554.606417-1-npiggin@gmail.com> In-Reply-To: <20260321144554.606417-1-npiggin@gmail.com> From: Alistair Francis Date: Wed, 25 Mar 2026 12:20:46 +1000 X-Gm-Features: AQROBzBEn4Crmvn43j_9IR6fZXWUvN_GG2TEs8scPR157S_PZTv5MrcJEJrk-zw Message-ID: Subject: Re: [PATCH v3 0/3] target/riscv: corner case fixes To: Nicholas Piggin Cc: qemu-riscv@nongnu.org, Laurent Vivier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org, Joel Stanley Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Mar 22, 2026 at 12:47=E2=80=AFAM Nicholas Piggin wrote: > > Changes: > v3: > * Added vloxei8.v to overflow test. > * Added store variants of interrupted vector ops tests. > > v2: > * Added a tcg tests build-time check for vector intrinsics support > in target compiler before building new tests that require it. > ci images may not support these yet unfortunately, but upgrading > those will be a separate effort. > > Thanks, > Nick > > > Nicholas Piggin (3): > target/riscv: Fix IALIGN check in misa write > target/riscv: Fix vector whole ldst vstart check > tests/tcg: Add riscv test for interrupted vector ops Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/csr.c | 16 +- > target/riscv/vector_helper.c | 2 + > tests/tcg/riscv64/Makefile.softmmu-target | 5 + > tests/tcg/riscv64/Makefile.target | 16 ++ > tests/tcg/riscv64/misa-ialign.S | 88 ++++++ > tests/tcg/riscv64/test-interrupted-v.c | 329 ++++++++++++++++++++++ > tests/tcg/riscv64/test-vstart-overflow.c | 78 +++++ > 7 files changed, 531 insertions(+), 3 deletions(-) > create mode 100644 tests/tcg/riscv64/misa-ialign.S > create mode 100644 tests/tcg/riscv64/test-interrupted-v.c > create mode 100644 tests/tcg/riscv64/test-vstart-overflow.c > > -- > 2.51.0 > >